Patents by Inventor Yu Chiang

Yu Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682557
    Abstract: A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: June 20, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Chih-Yu Chiang
  • Patent number: 11682710
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first metal gate structure in a first dielectric layer. The method includes forming a second metal gate structure in the first dielectric layer, and the second metal gate structure includes a second metal electrode over a second gate dielectric layer. The method also includes forming a mask structure covering the first metal gate structure. The method includes etching a portion of the second gate dielectric layer and a portion of the second metal electrode of the second metal gate structure to form a first conductive portion extending above a top surface of the second gate dielectric layer. The method includes forming a metal layer over the first conductive portion, and the metal layer has a recess, and a top portion of the first conductive portion extends into the recess.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang
  • Publication number: 20230133948
    Abstract: Examples of computing devices for adjusting a display setting of an external display device are described herein. In an example, a computing device may include a power delivery (PD) controller that may transmit the display setting to the external display device, upon detecting that the external display device is connected to the computing device. In an example, the display setting may be transmitted in accordance with a Universal Serial Bus (USB) PD protocol. Once the external display device has adjusted a display panel based on the display setting, an acknowledgement may be sent to the PD controller.
    Type: Application
    Filed: April 22, 2020
    Publication date: May 4, 2023
    Inventors: CHIA-CHENG LIN, HUNG-LUNG CHEN, SHAO-YU CHIANG
  • Publication number: 20230135084
    Abstract: Semiconductor structure and methods of forming the same are provided. A semiconductor structure according to the present disclosure include a substrate that includes a first region and a second region adjacent the first region, a first fin disposed over the first region, a second fin disposed over the second region, a first source/drain feature disposed over the first fin and a second source/drain feature disposed over the second fin, and an isolation structure disposed between the first fin and the second fin. The isolation structure has a protruding feature rising above the rest of the isolation structure and the protruding feature is disposed between the first fin and the second fin.
    Type: Application
    Filed: May 17, 2022
    Publication date: May 4, 2023
    Inventors: Hsin Yang Hung, Wei-Syuan Dai, Tsung-Yu Chiang, Lung Chen
  • Patent number: 11637018
    Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsinhsiang Tseng, Chi-Ruei Yeh, Tsung-Yu Chiang
  • Patent number: 11636902
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: April 25, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Publication number: 20230118769
    Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.
    Type: Application
    Filed: August 22, 2022
    Publication date: April 20, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yu-Ting Liu, Che-Yu Chiang, Deng-Fu Weng
  • Publication number: 20230083754
    Abstract: The present disclosure provides a probiotics of PTA22 from rabbits, a nutritional composition for preparing food of rabbits and a composition for rabbits to degrade oxalic acid. Through this disclosure, the health of rabbits can be ensured and the resistance to pathogenic bacteria can be improved after rabbits consume the food containing PTA22. As well, the probiotic PTA22 can help rabbits reduce the risk of hypercalciuria and calculus.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 16, 2023
    Inventors: JYH HORNG SHYU, LI YU CHIANG, YU HSIN CHANG, CHING YU CHIU, PEI-JU WANG
  • Publication number: 20230068485
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20230062370
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20230065797
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Chang-Jung HSUEH, Wei-Hung LIN, Kai Jun ZHAN, Wan-Yu CHIANG
  • Patent number: 11587790
    Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen, Chih-Yung Lin
  • Publication number: 20230048903
    Abstract: A signal modulation apparatus, a memory storage apparatus, and a signal modulation method are disclosed. The signal modulation apparatus includes an observation circuit, a signal modulation circuit, and a phase control circuit. The signal modulation circuit is configured to generate a second signal according to a first signal and a reference clock signal. A frequency of the first signal is different from a frequency of the second signal. The phase control circuit is configured to obtain an observation information via the observation circuit. The observation information reflects a process variation of at least one electronic component in the signal modulation apparatus. The phase control circuit is further configured to control an offset between the first signal and the reference clock signal according to the observation information.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 16, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Guan-Wei Wu, Jen-Chu Wu, Jen-Huo Wang, Yu-Chiang Liao, Shih-Yang Sun
  • Publication number: 20230046075
    Abstract: A liquid cooling system includes a liquid coolant conduit in proximity to heat-generating electrical components within an enclosed space. The conduit allows circulation of a liquid coolant to extract heat from the heat-generating components. The heat-generating components includes at least one first heat-generating electrical component and at least one second heat-generating electrical component. The first heat-generating component produces greater heat than the second heat-generating component. The enclosed space includes an inlet and an outlet. The conduit includes a nozzle fluidly connected to the inlet. The nozzle is located within the enclosed space. The nozzle forms first and second aperture sets. The first aperture set directs the liquid coolant to the first heat-generating component. The second aperture set directs the liquid coolant to the second heat-generating component.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 16, 2023
    Inventors: Chao-Jung CHEN, Yu-Nien HUANG, Chang-Yu CHIANG
  • Patent number: 11573919
    Abstract: A method for synchronous serial communication includes encoding, by a master device, a header field to be initially transmitted in a frame with a header identification code and a slave count value that defines a number of slave devices communicatively coupled to the master device. A plurality of address fields to be transmitted in the frame are also encoded by the master device. Each of the address fields corresponding to a different one the slave devices. A first of the address fields to be transmitted in the frame corresponds to a last of the slave devices to receive the header field, and a last of the address fields to be transmitted in the frame corresponds to a first of the slave devices to receive the header field. The frame is transmitted to the slave devices by the master device.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh Raja, Ishtiaque Amin, Kuang Yu Chiang, Ryan Kehr
  • Patent number: 11572898
    Abstract: A levering device includes a coupling block, a gripper, an operating rod, and a constraint sleeve. The coupling block includes a coupling chamber, two guide slots in communication with the coupling chamber, an extension rod, and an axial hole axially cut through the extension rod in communication with the coupling chamber. The operating rod being axially movably inserted through the axial hole into a bearing chamber of a housing of a motor-driven water lifting device to stop against respective one end of a wheel axle of the motor-driven water lifting device. The gripper is attachable to the two guide slots of the coupling block and includes two gripper blocks and two claw bars respectively connected to the gripper blocks. The constraint sleeve is sleeved onto the coupling block to stop the two claw bars in the respective the guide slots.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: February 7, 2023
    Assignee: NAN YANG WATER SCIENTIFIC TECHNOLOGY CO., LTD
    Inventors: Jui-Yu Lin, Po-Yu Chiang, Hsi Chen
  • Publication number: 20230014210
    Abstract: An adjustable wrench is disclosed. The adjustable wrench is used for an assembly part. The adjustable wrench includes a frame, an adjustable member, and an engaging element. The adjustable member is adjacent to the frame to form a space between an inner side of the frame, wherein the adjustable member further has a rack. The engaging element is adjacent to the adjustable member and has an engaging portion that meshes with the rack such that, after the adjustable member slides, a position of the engaging portion meshed with the rack is changed so as to change the size of the space; thus, the space can be adjusted to match assembly parts of different specifications.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 19, 2023
    Inventors: Chien-Chou Liao, Chien-Wei Huang, Wan-Yu Chiang
  • Publication number: 20220406085
    Abstract: A driving apparatus and an operation method thereof are provided. The driving apparatus includes a first driving circuit and a second driving circuit. The first driving circuit suspends performing at least one of a display driving operation and a touch sensing operation during a skip period under a driving mode, and the first driving circuit performs the at least one of the display driving operation and the touch sensing operation outside the skip period under the driving mode. The second driving circuit is coupled to the first driving circuit. The second driving circuit performs a fingerprint sensing operation during the skip period.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 22, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Wei-Lun Shih, Tsen-Wei Chang, Cho-Hsuan Jhang, Chih-Peng Hsia, Cheng-Yu Chiang
  • Patent number: D976894
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 31, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jen-Yu Chiang, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu
  • Patent number: D983634
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: April 18, 2023
    Assignee: Hanlong Industrial Co., Ltd.
    Inventor: Wan-Yu Chiang