Abstract: The present disclosure provides a bolometer including a substrate, a reflecting mirror on the substrate, and a temperature sensing unit above the reflecting mirror. The temperature sensing unit includes a first insulating layer, a thermistor on the first insulating layer, a second insulating layer on the thermistor, an electrode layer in the second insulating layer and right above the thermistor, and a metal meta-surface in the second insulating layer and right above the electrode layer. The electrode layer includes a plurality of electrodes separated from each other. A projection region of the metal meta-surface on the thermistor is equal to or larger than the thermistor.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad. The method determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in the standby mode is greater than or equal to a preset value. If the drop is greater than or equal to the preset value, the method then determines whether the drop in voltage falls in a preset range. If the drop falls in the preset range, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: Disclosed are an interposer substrate, a package structure and a manufacturing method of a package structure. In one embodiment, the interposer substrate includes a substrate, a bridge device in the substrate, a memory in the substrate and beside the bridge device and a through substrate via in the substrate and beside the bridge device and the memory.

Abstract: A capacitorless dynamic random access memory (DRAM) cell may include a plurality of transistors. At least a subset of the transistors may include a channel layer that approximately resembles an inverted U shape, an ohm symbol (?) shape, or an uppercase/capital omega (?) shape. The particular shape of the channel layer provides an increased channel length for the subset of the transistors, which may reduce the off current and may reduce current leakage in the subset of the transistors. The reduced off current and reduced current leakage may increase data retention in the subset of the transistors and/or may increase the reliability of the subset of the transistors without increasing the footprint of the subset of the transistors. Moreover, the particular shape of the channel layer enables the subset of the transistors to be formed with a top-gate structure, which provides low integration complexity with other transistors in the capacitorless DRAM cell.

Abstract: The fuse device includes a plurality of fuse circuits, a global latch circuit and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is used to sense the blown states of the fuse circuits at different times, so as to output the fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuits. Each of these local latch circuits latches the fuse information output by the global latch circuit at the different times.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: A capacitor structure including a silicon material layer, a support frame layer, and a capacitor is provided. The support frame layer is disposed in the silicon material layer. The support frame layer has recesses. There is a cavity between two adjacent recesses. The support frame layer is located between the cavity and the recess. The support frame layer has a through hole directly above the cavity. The capacitor is disposed in the silicon material layer. The capacitor includes a first insulating layer and a first electrode layer. The first insulating layer is disposed on the support frame layer. The first electrode layer is disposed on the first insulating layer and fills the recess and the cavity.

Abstract: A method of controlling a battery-powered remote controller to decrease a duty cycle to allow continued operations despite the quantity of the battery is bad determines a drop in voltage of the battery in standby mode as voltage of the battery is being read. When receiving a command to activate a voice function, determining whether the drop in voltage in standby mode is greater than or equal to a preset value. If yes, the method then determines whether the drop in voltage falls in a preset range. If yes, the method regulates a duty cycle of the pulse signal activating the voice function, and activates the voice function as required. A remote controller and a non-transitory storage medium are also provided.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: A high-power edge-emitting semiconductor laser with asymmetric structure, comprising: a substrate layer; a lower cladding layer; a lower optical waveguide layer; a first lower barrier layer; a quantum well layer; a first upper barrier layer; an upper optical waveguide layer, and make the thickness of the upper optical waveguide layer be below 300 nm, the thickness of the upper optical waveguide layer is ?˜½ of the thickness of the lower optical waveguide layer; an upper cladding layer, and make the thickness of the upper cladding layer be below 900 nm, the thickness of the upper cladding layer is ?˜½ of the thickness of the lower cladding layer; and an ohmic contact layer formed on the upper cladding layer.

Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.

Abstract: Embodiments of the present disclosure provides a solution to address any issues caused by non-uniform channel heights across a substrate. Particularly, an isolation layer is selectively implanted to alter etching rate of the isolation layer around semiconductor fin structures prior to STI recess.