Patents by Inventor Yu Chu

Yu Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255249
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Keng-Chu Lin, Yu-Yun Peng
  • Patent number: 12255239
    Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal Abhijith Khaderbad, Keng-Chu Lin, Yu-Yun Peng
  • Patent number: 12253489
    Abstract: A gas sensor includes a first electrode, a gas detecting layer disposed on the first electrode, and an electric-conduction enhanced electrode unit being electrically connected to the first electrode and the gas detecting layer. The electric-conduction enhanced electrode unit includes an electric-conduction enhancing layer and a second electrode electrically connected to the electric-conduction enhancing layer. The electric-conduction enhancing layer is electrically connected to the gas detecting layer and is made of an electrically conductive organic material.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 18, 2025
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsiao-Wen Zan, Hsin-Fei Meng, Yu-Chi Lin, Shang-Yu Yu, Ting-Wei Tung, Yi-Chu Wu, Yu-Nung Mao
  • Publication number: 20250087257
    Abstract: A circuit module with improved timing control, may comprise a functional circuit, a control circuit, a main auxiliary circuit and an additional auxiliary circuit. The control circuit may control operation timing of the functional circuit according to response characteristics of a first node. When enabled, the main auxiliary circuit may provide main conduction path(s) between the first node and a base node. Respectively when enabled and disabled, the additional auxiliary circuit may provide and not provide additional conduction path(s) between the first node and the base node. When the control circuit controls the operation timing of the functional circuit, the main auxiliary circuit may be enabled, and the additional auxiliary circuit may be disabled or enabled according to whether a mode signal is of a first mode level or a second level.
    Type: Application
    Filed: September 10, 2024
    Publication date: March 13, 2025
    Inventors: Po-Yu WU, Li-Wei Chu, Nan-Chun Lien
  • Publication number: 20250087536
    Abstract: A deposition system provides a feature that may reduce costs of the sputtering process by increasing a target change interval. The deposition system provides an array of magnet members which generate a magnetic field and redirect the magnetic field based on target thickness measurement data. To adjust or redirect the magnetic field, at least one of the magnet members in the array tilts to focus on an area of the target where more target material remains than other areas. As a result, more ion, e.g., argon ion bombardment occurs on the area, creating more uniform erosion on the target surface.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hao CHENG, Hsuan-Chih CHU, Yen-Yu CHEN, Yi-Ming DAI
  • Patent number: 12249657
    Abstract: In some implementations, one or more semiconductor processing tools may form a first terminal of a semiconductor device by depositing a tunneling oxide layer on a first portion of a body of the semiconductor device, depositing a first volume of polysilicon-based material on the tunneling oxide layer, and depositing a first dielectric layer on an upper surface and a second dielectric layer on a side surface of the first volume of polysilicon-based material. The one or more semiconductor processing tools may form a second terminal of the semiconductor device by depositing a second volume of polysilicon-based material on a second portion of the body of the semiconductor device. A side surface of the second volume of polysilicon-based material is adjacent to the second dielectric layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chu Lin, Chi-Chung Jen, Wen-Chih Chiang, Ming-Hong Su, Yung-Han Chen, Mei-Chen Su, Chia-Ming Pan
  • Publication number: 20250081492
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes removing a first semiconductor layer disposed between a second semiconductor layer and a third semiconductor layer and performing an oxide refill process to form a seamless dielectric material between the second and third semiconductor layers. The oxide refill process includes exposing the second and third semiconductor layers to a silicon-containing precursor at a first flow rate for a first duration to form a monolayer, and exposing the monolayer to an oxygen-containing precursor at a second flow rate for a second duration to form the seamless dielectric material, the second flow rate is about twice to about 20 times the first flow rate, and the second duration is about twice to about 20 times the first duration.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventors: Kuei-Lin CHAN, Wei-Ting YEH, Fu-Ting YEN, Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20250072039
    Abstract: A semiconductor structure includes a first circuit area having first fin active regions extending lengthwise along a first direction, each of the first fin active regions includes first channel regions; a second circuit area having second fin active regions extending lengthwise along the first direction, each of the second fin active regions includes second channel regions; a gate connector area between and separating the first and the second circuit areas, the gate connector area having filter fins extending lengthwise along the first direction; and a gate structure extending across the first circuit area, the gate connector area, and the second circuit area along a second direction over the first and second channel regions and the filter fins. A portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas.
    Type: Application
    Filed: January 24, 2024
    Publication date: February 27, 2025
    Inventors: Yi-Hong Wang, Hui-Hsuan Kung, Tien Yu Chu, Chih-Hsiao Chen, Yi-Chen Li
  • Publication number: 20250072135
    Abstract: A semiconductor device, and method of fabricating the same, includes a first substrate, the first substrate including at least one visible light photosensor disposed between a first side and a second side of the first substrate, a second substrate including an infrared light photosensor disposed between a second side of the second substrate and a first side of the second substrate, and a metalens disposed between the visible light photosensor and the infrared light photosensor, the metalens configured to focus infrared light impinging on a surface of the first substrate onto the infrared light photosensor.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Cheng-Yu Huang, Wei-Chieh Chiang, Dun-Nian Yaung
  • Patent number: 12237800
    Abstract: An electric window covering has a covering material, a driving device, a microcontroller, a position detecting module and a trigger detecting module. The position detecting module detects a position of a lower end of the covering material to generate a position information. The microcontroller compares the position information with a reference position to generate a position relationship with respect to the reference position. The trigger detecting module detects whether the covering material is moved by an external force for generating a detecting result. When the microcontroller determines that a trigger event is received according to the detecting result, the microcontroller configures the driving device to move the covering material according to the position relationship and the trigger event.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: February 25, 2025
    Assignee: Nien Made Enterprise Co., Ltd.
    Inventors: Chao-Hung Nien, Jui-Pin Jao, Ping-Yu Chu
  • Patent number: 12233368
    Abstract: A device for removing particles in a gas stream includes a first cylindrical portion configured to receive the gas stream containing a target gas and the particles, a rotatable device disposed within the first cylindrical portion and configured to generate a centrifugal force when in a rotational action to divert the particles away from the rotatable device, a second cylindrical portion coupled to the first cylindrical portion and configured to receive the target gas, and a third cylindrical portion coupled to the first cylindrical portion and surrounding the second cylindrical portion, the third cylindrical portion being configured to receive the diverted particles.
    Type: Grant
    Filed: August 13, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hao Cheng, Hsuan-Chih Chu, Yen-Yu Chen
  • Patent number: 12238864
    Abstract: An electronic apparatus including a compression molding board and a connection pad is provided. The compression molding board has a device bonding area and a bending area formed by compression molding. The device bonding area is different from the bending area. The connection pad is disposed on the device bonding area of the compression molding board.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 25, 2025
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Lin Hsu, Kuan-Chu Wu, Ting-Yu Ke, Min-Hsiung Liang, Yu-Ming Peng
  • Patent number: 12235409
    Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: February 25, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
  • Patent number: 12237369
    Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: February 25, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Huixian Lai, Yu Cheng Tung, Chao-Wei Lin, Chiayi Chu
  • Patent number: 12235410
    Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: February 25, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Wen-Yu Tsai, Chien-Pang Chang, Chi-Wei Chi, Wei-Fong Hong, Chun-Hung Teng, Kuo-Chiang Chu
  • Publication number: 20250063956
    Abstract: A semiconductor structure includes a ferroelectric layer and a semiconductor layer. Thee ferroelectric layer has a first surface and a second surface opposite to the first surface. The semiconductor layer is formed on one of the first surface and the second surface.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu CHEN, Sheng-Hung SHIH, Kuo-Chi TU, Wen-Ting CHU, Kuo-Ching HUANG, Harry-Haklay CHUANG
  • Publication number: 20250046164
    Abstract: Provided are a method and system for interactively searching for a target object and a storage medium. The method includes: obtaining a first interactive instruction from a first terminal; determining a target object corresponding to the first interactive instruction; obtaining target information of the target object; where the target information includes at least one of: a current position of the target object, picture information of the current position, a historical trajectory of the target object, a navigation route, or any combination thereof; sending the target information to the first terminal such that the first terminal displays the target information.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 6, 2025
    Inventors: Ning ZHANG, Yu GU, Yue LI, Xiaozhen JIA, Fanhao KONG, Xiao CHU
  • Publication number: 20250048647
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
  • Patent number: 12216332
    Abstract: An imaging lens assembly has an optical axis and includes a plastic lens element set. The plastic lens element set includes two plastic lens elements and at least one anti-reflective layer. The two plastic lens elements, in order from an object side to an image side along the optical axis are a first plastic lens element and a second plastic lens element. The anti-reflective layer has a nanostructure and is disposed on at least one of an image-side surface of the first plastic lens element and an object-side surface of the second plastic lens element.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: February 4, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chien-Pang Chang, Wen-Yu Tsai, Lin-An Chang, Ming-Ta Chou, Kuo-Chiang Chu
  • Patent number: 12216090
    Abstract: A device is provided for blade detection. The device comprises a supporting frame, a linear track, and a fixture. The supporting frame comprises a plurality of aluminum extruded bodies with connectors thereof and a plurality of rotating adjusting pads with fixing plates thereof; the linear track comprises a plurality of tracks with connectors thereof and a plurality of sliders; and the fixture comprises a bearing holder part, a bearing connector, a sliding rod, a joint bearer with a connector thereof, a chuck, and a detector. On detecting a blade, the present invention helps the detector to be maintained on the blade surface for detection in horizontal and vertical directions without deviating from track; and the detector is in contact with the blade surface to move precisely and regularly without missing or repeating detection areas. Thus, the area is detected completely with time saved and accuracy improved.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 4, 2025
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R. O.C.
    Inventors: Yu-Chu Lin, Wei-Nian Su