Abstract: Devices and methods are disclosed for managing and/or treating body tissues obstructing a hollow body lumen, including the prostatic lobe tissues obstructing the urethra, for example conditions including benign prostatic hyperplasia (BPH), bladder outlet obstruction (BOO), benign prostatic obstruction (BPO) and associated lower urinary tract symptoms (LUTS). A prostatic implant deployment and delivery system may have a controlled release mechanism, a handle mechanism and an irrigation system. The controlled release mechanism includes a disengageable connection between a pusher member and the prostatic implant with a control member. The handle mechanism includes a plunger for advancing the pusher member and an actuator for withdrawing the control member. The irrigation system may define two fluid paths.

Abstract: A broadband measurement system and a measurement method for broadband property are provided. The signal measurement apparatus is used to transmit a measuring signal belonging to a first frequency domain from its measuring port. Two ports of the signal converter are used to connect with two measuring ports of the signal measurement apparatus. The first passive mixer of the signal converter is configured as bidirectional, and the second passive mixer of the signal converter is configured as bidirectional. Two mixers are used to convert the signals from the first frequency domain into a second frequency domain, and convert the signals from the second frequency domain into the first frequency domain.

Abstract: Herein disclosed are a micro-component transfer head, a micro-component transfer device, and a micro-component display. Said micro-component transfer head comprises a carrying surface that corresponds to a micro-component extraction area. Said extraction area conforms with a first geometric object, which comprises at least an acute angle. A second geometric object comprises at least a right angle and is constituted of n copies of the first geometric object, n being an integer greater than 1. The shape of the first geometric object differs from that of the second.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: The present disclosure relates to methods and associated systems for operating a battery exchange station. The present method includes (1) receiving a ratio associated with a plurality of vehicles served by the battery exchange station; and (2) based on the ratio, storing different sets of information in memories associated with the batteries respectively, in accordance with received ratio.

Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.

Abstract: A permanent magnet motor is provided, including: a stator and a rotor. The stator has a plurality of windings. The rotor has a plurality of magnet placement slots and a plurality of air gaps. The plurality of magnet placement slots include a plurality of circumferential magnet placement slots circumferentially arranged and a plurality of radial magnet placement slots radially extending. The circumferential magnet placement slots and the radial magnet placement slots are circumferentially alternately arranged. The plurality of air gaps are adjacent to part of the plurality of magnet placement slots and distributed to be on a d-axis flux path of the rotor.

Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

Abstract: A centralized dynamic resource allocation is suggested to adjust a resource allocation for at least two DPUs. Also, a method for adjusting a resource allocation for the at least two DPUs by a centralized dynamic resource allocation entity is provided. Further, a system comprising at least one such device is proposed.

Abstract: Devices and methods are disclosed for determining prostatic urethral length. A measuring device having an elongated shaft member with associated markings may be advanced through a working channel of the cystoscope so that a positioning aid disposed on the elongated shaft member is located at a bladder neck of the patient. A first position of the elongated shaft member is determined using the markings. The elongated shaft member is then withdrawn to a second position at which the positioning aid is located at the patient's verumontanum. The prostatic urethral length is determined based at least in part on relative translational movement of the elongated shaft member between the first position and the second position using the markings.

Abstract: Devices and methods are disclosed for determining prostatic urethral length. A measuring device having an elongated shaft member with associated markings may be advanced through a working channel of the cystoscope so that a positioning aid disposed on the elongated shaft member is located at a bladder neck of the patient. A first position of the elongated shaft member is determined using the markings. The elongated shaft member is then withdrawn to a second position at which the positioning aid is located at the patient's verumontanum. The prostatic urethral length is determined based at least in part on relative translational movement of the elongated shaft member between the first position and the second position using the markings.

Abstract: Devices and methods are disclosed for determining prostatic urethral length. A measuring device having an elongated shaft member with associated markings may be advanced through a working channel of the cystoscope so that a positioning aid disposed on the elongated shaft member is located at a bladder neck of the patient. A first position of the elongated shaft member is determined using the markings. The elongated shaft member is then withdrawn to a second position at which the positioning aid is located at the patient's verumontanum. The prostatic urethral length is determined based at least in part on relative translational movement of the elongated shaft member between the first position and the second position using the markings.

Abstract: An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a skew adjusting circuit. The ADC circuits convert an input signal according to clock signals, to generate first quantized outputs. The calibration circuit calibrates the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes an estimating circuit and a feedback circuit. The estimating circuit analyzes the second quantized outputs to generate detection signals, wherein the detection signals are related to time difference information of the clock signals. The skew adjusting circuit outputs the detection signals as adjustment signals, wherein the adjustment signals are configured to reduce a clock skew of the ADC circuits. The feedback circuit analyzes the detection signals generated by the estimating circuit, to generate a feedback signal to the estimating circuit, wherein the estimating circuit is configured to adjust the detection signals according to the feedback signal.

Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

Abstract: A light-emitting device includes an epitaxial structure, and first and second electrodes. The epitaxial structure has a first surface and a second surface opposite to each other, first dislocation density regions and second dislocation density regions. The first dislocation density regions and the second dislocation density regions are alternately disposed between the first surface and the second surface. A dislocation density of each first dislocation density region is lower than a dislocation density of each second dislocation density region and a quantity of the first dislocation density regions is at least ten. The epitaxial structure further includes a light-emitting layer, a first-type semiconductor layer and a second-type semiconductor layer disposed on two opposite sides of the light-emitting layer. The first electrode and the second electrode are electrically connected to the first-type semiconductor layer and the second-type semiconductor layer, respectively.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.