Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: The present disclosure provides a method of chemical mechanical polish operation and a chemical mechanical polish operation system. The method includes obtaining a first input parameter and a second input parameter, wherein the first input parameter is associated with an additive of a slurry, and the second input parameter is associated with a characteristic of a process apparatus, determining an output parameter associated with the process apparatus based on the first input parameter and the second input parameter, securing a workpiece by a head over a platen in the process apparatus, supplying the slurry with the additive over the platen with the additive configured with the first parameter, and polishing a surface of the workpiece by operating the process apparatus configured with the output parameter.

Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Abstract: Provided herein are methods, kits, and devices related to genetic variations of neurological disorders. For example, methods, kits, and devices for using such genetic variations to assess susceptibility of developing Alzheimer's disease.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: Techniques for managing access to physical assets based on captured digital data and a database are provided. In one technique, one or more functions in an application that executes on a client device are locked. A smart badge that is associated with healthcare information is then received from a remote server system. In response to receiving the smart badge, the one or more functions are unlocked. After unlocking the one or more functions and in response to user input that selects a particular function of the one or more functions, a request and identification data that pertain to the particular function are transmitted over a computer network.

Abstract: A micro LED display panel includes a driving substrate and a plurality of micro light emitting diodes (LEDs). The driving substrate has a plurality of pixel regions. Each of the pixel regions includes a plurality of sub-pixel regions. The micro LEDs are located on the driving substrate. At least one of the sub-pixel regions is provided with two micro LEDs of the micro LEDs electrically connected in series, and a dominant wavelength of the two micro LEDs is within a wavelength range of a specific color light. In a repaired sub-pixel region of the sub-pixel regions, only one of the two micro LEDs emits light. In a normal sub-pixel region of the sub-pixel regions, both of the two micro LEDs emit light.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: The present disclosure provides a method for screening, isolating and purifying analytes.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. An original image of the display is received and segmented into region of interest (ROI) patches. A predetermined range of spatial frequency components are filtered out from the ROI patches to generate filtered ROI patches. A mura defect is identified from the display according to the filtered ROI patches and predetermined mura patterns.

Abstract: A device is provided for blade detection. The device comprises a supporting frame, a linear track, and a fixture. The supporting frame comprises a plurality of aluminum extruded bodies with connectors thereof and a plurality of rotating adjusting pads with fixing plates thereof; the linear track comprises a plurality of tracks with connectors thereof and a plurality of sliders; and the fixture comprises a bearing holder part, a bearing connector, a sliding rod, a joint bearer with a connector thereof, a chuck, and a detector. On detecting a blade, the present invention helps the detector to be maintained on the blade surface for detection in horizontal and vertical directions without deviating from track; and the detector is in contact with the blade surface to move precisely and regularly without missing or repeating detection areas. Thus, the area is detected completely with time saved and accuracy improved.

Abstract: A burr trimming device includes a removing assembly and a directed spraying assembly disposed on a carrier, wherein the directed spraying assembly has a nozzle facing the removing assembly. The directed spraying assembly rapidly freezes objects such as burrs and then the removing assembly removes the hardened objects by coming into rigid contact therewith, thereby ensuring complete removal of the fine flexible burrs.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A micro light-emitting device display apparatus includes a driving substrate and a plurality of micro light-emitting devices. The micro light-emitting devices are disposed on the driving substrate. The micro light-emitting devices include a plurality of first, second and third micro light-emitting devices. Each of the first, the second and the third micro light-emitting devices respectively has a plurality of first, second, and third light-emitting regions independently controlled. A first light-emitting region of a first micro light-emitting device, a second light-emitting region of a second micro light-emitting device, and a third light-emitting region of a third micro light-emitting device are located in a first pixel region. A first light-emitting region of another first micro light-emitting device, a second light-emitting region of another second micro light-emitting device, and another third light-emitting region of the third micro light-emitting device are located in a second pixel region.

Abstract: An arcuate display device, including an arcuate display surface, a plurality of display units, an image source, and a controller, is provided. The display units are configured on the arcuate display surface in an array manner, and each of the display units includes a plurality of pixels. The controller is configured to receive a plurality of pixel signals from the image source to generate a plurality of frame signals respectively corresponding to the display units. Each of the frame signals includes the pixel signals, a plurality of first dummy signals, and a plurality of second dummy signals, in which the pixel signals respectively correspond to the pixels. A sum of an amount of the pixel signals, an amount of the first dummy signals, and an amount of the second dummy signals in each of the frame signals is same. A driving method of the arcuate display device is also provided.

Abstract: A window covering includes a housing, a covering material, a spindle, and a driving device. The spindle and the driving device are provided at the housing. The driving device includes a motor having a shaft, and an epicyclic gearing decelerating device having an input end and an output end connected to the shaft and the spindle, respectively. Whereby, the spindle can drive the covering material to expand or to collapse. The epicyclic gearing decelerating device includes a ring portion and at least a planet gear assembly which is coupled between the input end and the output end. The planet gear assembly includes a plurality of planet gears having a Shore A durometer hardness of 45-90, which is rotatable along the fixedly provided ring portion. While being driven to move, a lower end of the covering material moves at a speed higher than 65 mm per second.