Patents by Inventor Yu Der Chih

Yu Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12041860
    Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Wen-Zhang Lin, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Chrong-Jung Lin, Ya-Chin King, Cheng-Jun Lin, Wang-Yi Lee
  • Patent number: 12026404
    Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih, Yih Wang
  • Patent number: 12027205
    Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 12009029
    Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Meng-Fan Chang, May-Be Chen, Cheng-Xin Xue, Je-Syu Liu
  • Publication number: 20240170031
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 23, 2024
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Patent number: 11984162
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
  • Publication number: 20240153559
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 9, 2024
    Inventors: Yu-Der CHIH, Chung-Cheng CHOU, Wen-Ting CHU
  • Publication number: 20240153558
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Patent number: 11978518
    Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Chieh Chen, Cheng-Hsiung Kuo, Yu-Der Chih
  • Patent number: 11973502
    Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
  • Patent number: 11961546
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Patent number: 11962693
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 11943936
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Der Chih, May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen Zhang Lin, Chrong Jung Lin, Ya-Chin King, Chieh Lee, Wang-Yi Lee
  • Patent number: 11923036
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Patent number: 11922108
    Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsiang Weng, Yu-Der Chih
  • Patent number: 11915754
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 11915752
    Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
  • Publication number: 20240046968
    Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
  • Publication number: 20240036597
    Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
  • Publication number: 20240028451
    Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
    Type: Application
    Filed: August 4, 2023
    Publication date: January 25, 2024
    Inventors: Hiroki NOGUCHI, Yu-Der CHIH, Hsueh-Chih YANG, Randy OSBORNE, Win San KHWA