Patents by Inventor Yu Der Chih
Yu Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11755410Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.Type: GrantFiled: July 26, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C. Y. Wang
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Publication number: 20230282287Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bitline.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventor: YU-DER CHIH
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Publication number: 20230273752Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih, Yih Wang
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Patent number: 11742024Abstract: A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.Type: GrantFiled: May 27, 2020Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Der Chih, Cheng-Hsiung Kuo, Chung-Chieh Chen
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Patent number: 11742021Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.Type: GrantFiled: July 26, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Hiroki Noguchi, Yu-Der Chih, Yih Wang
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Publication number: 20230268909Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.Type: ApplicationFiled: May 1, 2023Publication date: August 24, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
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Patent number: 11735263Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.Type: GrantFiled: July 22, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
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Patent number: 11735238Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.Type: GrantFiled: June 30, 2022Date of Patent: August 22, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
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Publication number: 20230260559Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventor: Yu-Der Chih
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Publication number: 20230253040Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang, Yun-Sheng Chen, May-Be Chen, Ya-Chin King, Wen Zhang Lin, Chrong Lin, Hsin-Yuan Yu
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Publication number: 20230253041Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.Type: ApplicationFiled: April 20, 2023Publication date: August 10, 2023Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Patent number: 11720130Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.Type: GrantFiled: August 9, 2021Date of Patent: August 8, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yen-An Chang, Chieh-Pu Lo, Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
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Patent number: 11714717Abstract: A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.Type: GrantFiled: March 24, 2022Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
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Publication number: 20230240156Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.Type: ApplicationFiled: January 21, 2022Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der CHIH, Wen-Zhang LIN, Yun-Sheng CHEN, Jonathan Tsung-Yung CHANG, Chrong-Jung LIN, Ya-Chin KING, Cheng-Jun LIN, Wang-Yi LEE
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Publication number: 20230236929Abstract: A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.Type: ApplicationFiled: March 14, 2023Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
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Publication number: 20230230635Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuhsiang CHEN, Shao-Yu CHOU, Chun-Hao CHANG, Min-Shin WU, Yu-Der CHIH
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Publication number: 20230223080Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der CHIH, Meng-Fan CHANG, May-Be CHEN, Cheng-Xin XUE, Je-Syu LIU
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Patent number: 11693560Abstract: An in-memory computing device includes in some examples a two-dimensional array of memory cells arranged in rows and columns, each memory cell made of a nine-transistor current-based SRAM. Each memory cell includes a six-transistor SRAM cell and a current source coupled by a switching transistor, which is controlled by input signals on an input line, to an output line associates with the column of memory cells the memory cell is in. The current source includes a switching transistor controlled by the state of the six-transistor SRAM cell, and a current regulating transistor adapted to generate a current at a level determined by a control signal applied at the gate. The control signal can be set such that the total current in each output line is increased by a factor of 2 in each successive column of the memory cells.Type: GrantFiled: January 22, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Der Chih, Chi-Fu Lee, Jonathan Tsung-Yung Chang
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Publication number: 20230207005Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.Type: ApplicationFiled: May 31, 2022Publication date: June 29, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih
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Patent number: 11688436Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.Type: GrantFiled: May 31, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ku-Feng Lin, Yu-Der Chih