Patents by Inventor Yu Der Chih

Yu Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210409233
    Abstract: Disclosed herein is related to physical unclonable function (PUF) with enhanced security based on one time programmable (OTP) memory device. In one aspect, indirection process, hashing or a combination of them can be employed to hide a key for allowing access to an integrated circuit. Each indirection process may include identifying a subsequent address of the OTP memory device based on content stored by the OTP memory device at an address, and obtaining subsequent content stored by the OTP memory device at the subsequent address. Through a number of indirection processes, hidden content stored by the OTP memory device can be obtained. In one approach, hashing can be applied to input bits to obtain an address of the OTP memory device to apply. In one approach, hashing can be applied to the hidden content stored by the OTP memory device to generate the key.
    Type: Application
    Filed: April 13, 2021
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shih-Lien Linus Lu, Saman Adham, Yu-Der Chih
  • Publication number: 20210407594
    Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
    Type: Application
    Filed: November 24, 2020
    Publication date: December 30, 2021
    Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
  • Patent number: 11211106
    Abstract: A device includes a first reference storage unit, a second reference storage unit, a first reference switch, and a second reference switch. The first reference switch includes a first terminal coupled to a first reference bit line, a second terminal coupled to the first reference storage unit, and a control terminal coupled a reference word line. The second reference switch includes a first terminal coupled to a second reference bit line, a second terminal coupled to the second reference storage unit, and a control terminal coupled the reference word line. The first reference storage unit is configured to receive a bit data through the first reference switch, and to generate a first signal having a first logic state.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Fu Lee, Yu-Der Chih, Hon-Jarn Lin, Yi-Chun Shih
  • Patent number: 11211142
    Abstract: Memory devices and methods of repairing a memory are provided. A first array includes normal memory cells, and a second array includes repair memory cells. The repair memory cells are configured to be used in place of the normal memory cells. A look-up table comprises memory bitcells configured to store a set of entries including addresses of defective memory cells of the normal memory cells. A match circuit is configured to evaluate whether an input memory address is stored as a defective address in the memory bitcells. The match circuit is also configured to generate a selection signal for selecting the normal memory cells or the repair memory cells based on the evaluation.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Chun Shih, Po-Hao Lee, Chia-Fu Lee, Yu-Der Chih, Yu-Lin Chen
  • Patent number: 11204826
    Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win San Khwa
  • Publication number: 20210391018
    Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventor: YU-DER CHIH
  • Patent number: 11195562
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Publication number: 20210375363
    Abstract: A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Yu-Der CHIH, Cheng-Hsiung KUO, Chung-Chieh CHEN
  • Publication number: 20210365060
    Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An CHANG, Chieh-Pu LO, Yi-Chun SHIH, Chia-Fu LEE, Yu-Der CHIH
  • Publication number: 20210358532
    Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20210350836
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Publication number: 20210343333
    Abstract: Memories are provided. A memory includes a first memory array, a second memory array and a read circuit. The first memory array is configured to store first data. The second memory array is configured to store second data that is complementary to the first data. The read circuit includes a decoding circuit, a sensing circuit and an output buffer. The decoding circuit is configured to provide a first signal according to the first data and a second signal according to the second data in response to an address signal. The sensing circuit is configured to provide a first sensing signal according to a reference signal and the first signal, and a second sensing signal according to the reference signal and the second signal. The output buffer is configured to provide the first sensing signal or the second sensing signal as an output according to a control signal.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuhsiang CHEN, Shao-Yu CHOU, Chun-Hao CHANG, Min-Shin WU, Yu-Der CHIH
  • Patent number: 11151296
    Abstract: A memory cell array includes a first column of memory cells, a second column of memory cells, a first bit line, a second bit line and a source line. The second column of memory cells is separated from the first column of memory cells in a first direction. The first column of memory cells and the second column of memory cells are arranged in a second direction. The first bit line is coupled to the first column of memory cells, and extends in the second direction. The second bit line is coupled to the second column of memory cells, and extends in the second direction. The source line extends in the second direction, is coupled to the first column of memory cells and the second column of memory cells.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Hsiang Weng, Yu-Der Chih
  • Patent number: 11145388
    Abstract: A memory device that includes a memory array, a program circuit, a verify circuit and a controller is introduced. The program circuit is configured to apply a program pulse to at least one memory cell to set the at least one memory cell to a target state. The verify circuit is configured to perform a verify operation to determine whether the at least one memory cell reaches the predetermine threshold and to determine a number of failed memory cells among the at least one memory cell in response to determining that at least one of the at least one memory cell does not reach the target state. The controller is configured to adjust the program pulse according to the number of the failed memory cells to generate an adjusted program pulse that is applied to the failed memory cells to set the failed memory cells to the target state.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Der Chih
  • Patent number: 11137785
    Abstract: In an embodiment, a voltage regulation circuit includes a regulation circuit with a voltage regulator that provides an output voltage and a control circuit, coupled to the voltage regulator. The control circuit pulls up the output voltage to a reference voltage responsive to the control circuit detecting that a first voltage level of the output voltage is lower than a predefined voltage level. The control circuit decouples the output voltage from the reference voltage responsive to the control circuit detecting that the first voltage level of the output voltage is higher than the predefined voltage level.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yen-An Chang, Chieh-Pu Lo, Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • Patent number: 11139017
    Abstract: An integrated circuit device is provided. The integrated circuit device includes: a functional device including a selection device; and a bias generator circuit coupled to the selection device and configured to detect a leakage current of the functional device and generate a bias voltage based on the detected leakage current. The bias voltage is provided to the selection device to control the selection device.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-An Chang, Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih
  • Publication number: 20210306148
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 30, 2021
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20210294368
    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Yen-An CHANG, Chia-Fu LEE, Yu-Der CHIH, Yi-Chun SHIH
  • Publication number: 20210280245
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: Yu-Der CHIH, Chung-Cheng CHOU, Wen-Ting CHU
  • Publication number: 20210271417
    Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
    Type: Application
    Filed: August 5, 2020
    Publication date: September 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hiroki Noguchi, Shih-Lien Linus Lu, Yu-Der Chih, Yih Wang