Patents by Inventor Yu Der Chih

Yu Der Chih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sense amplifier
    Patent number: 11367468
    Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Fu Lee, Hon-Jarn Lin, Yu-Der Chih
  • MEMORY CIRCUIT, METHOD, AND ELECTRONIC DEVICE FOR IMPLEMENTING TERNARY WEIGHT OF NEURAL CELL NETWORK
    Publication number: 20220165334
    Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method for implementing a ternary weight for in-memory computing. According to an aspect of the disclosure, the memory circuit includes a first memory cell having a first resistor; a second memory cell having a second resistor, a write driver configured to set the first resistor to a first resistance value, a second write driver configured to set the second resistor to a second resistance value, a differential current sensing circuit configured to determine a differential current between the first memory cell and the second memory cell based on the first resistance value and the second resistance value, and a ternary weight detector configured to determine a ternary weight which is selected among a first ternary weight, a second ternary weight, and a third ternary weight based on the differential current.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Der Chih
  • SENSE AMPLIFIER AND OPERATING METHOD FOR NON-VOLATILE MEMORY WITH REDUCED NEED ON ADJUSTING OFFSET TO COMPENSATE THE MISMATCH
    Publication number: 20220157351
    Abstract: A sense amplifier includes a voltage comparator with offset compensation, a first clamping device and a second clamping device. The voltage comparator is coupled to a bit line and a reference bit line respectively, and configured to compare a first input voltage and a second input voltage to output a sensing signal. The first clamping circuit and the second clamping circuit trim a voltage corresponding to the bit line and a voltage corresponding to the reference bit line respectively to match the voltage corresponding to the reference bit line with the voltage corresponding to the bit line.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ku-Feng Lin, Yu-Der Chih
  • BACK-UP AND RESTORATION OF REGISTER DATA
    Publication number: 20220157355
    Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 19, 2022
    Inventor: Yu-Der Chih
  • Memory device and methods for programming and reading memory device
    Patent number: 11327860
    Abstract: A memory device and methods for programming and reading a memory device are provided. The memory device includes a memory array and a memory controller. The memory array includes a plurality of one-time programmable (OTP) cells, in which the OTP cells comprises a plurality of data cells for storing data, a plurality of supplementary cells in parallel to the data cells, and one or more redundant cells for each of a plurality of sets of the data cells. The memory controller is configured to program the data cells. The memory controller verifies and records a state of each data cell in a set of the data cells in the corresponding supplementary cell after the programming, and stores the data to be programmed to the data cell using the one or more redundant cells reserved for the set of the data cells when the data cell is verified as failed.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Jonathan Tsung-Yung Chang
  • RRAM voltage compensation
    Patent number: 11309022
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 19, 2022
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • MEMORY ERROR DETECTION AND CORRECTION
    Publication number: 20220114046
    Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Hiroki Noguchi, Yu-Der Chih, Hsueh-Chih Yang, Randy Osborne, Win-San Khwa
  • MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF
    Publication number: 20220115051
    Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Fu LEE, Yu-Der CHIH, Hon-Jarn LIN, Yi-Chun SHIH
  • Method of correcting errors in a memory array and method of screening weak bits in the same
    Patent number: 11294764
    Abstract: A method of screening weak bits in a memory array. The method includes storing a first set of data in a first memory array of the memory array, performing a first baking process on at least the first memory array or applying a first magnetic field to at least the first memory array, tracking an address of at least a first memory cell of a first set of memory cells of the first memory array, if the first memory cell of the first set of memory cells stores altered data, and at least one of replacing the first memory cell of the first set of memory cells storing the altered data with a corresponding memory cell in a second memory array of the memory array, or discarding the first memory cell of the first set of memory cells storing the altered data.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chia-Fu Lee, Chien-Yin Liu, Yi-Chun Shih, Kuan-Chun Chen, Hsueh-Chih Yang, Shih-Lien Linus Lu
  • Back-up and restoration of register data
    Patent number: 11295792
    Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Der Chih
  • MEMORY SENSE AMPLIFIER TRIMMING
    Publication number: 20220093142
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 24, 2022
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih
  • One time programmable memory
    Patent number: 11276469
    Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yu-Der Chih
  • Memory Cell Including Programmable Resistors With Transistor Components
    Publication number: 20220068378
    Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
    Type: Application
    Filed: June 3, 2021
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Der Chih, Maybe Chen, Yun-Sheng Chen, Wen Zhang Lin, Jonathan Tsung-Yung Chang, Chrong Jung Lin, Ya-Chin King, Hsin-Yuan Yu
  • Computing-In-Memory Architecture
    Publication number: 20220068328
    Abstract: Systems and methods are provided for a computing-in memory circuit that includes a bit line and a plurality of computing cells connected to the bit line. Each of the plurality of computing cells includes a memory element, having a data output terminal; a logic element, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the data output terminal of the memory element, the second input terminal receives a select signal; and a capacitor, having a first terminal and a second terminal, where the first terminal is coupled to the output terminal of the logic element, the second terminal is coupled to the bit line. A voltage of the bit line is driven by the plurality of computing cells.
    Type: Application
    Filed: June 3, 2021
    Publication date: March 3, 2022
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih, Jonathan Tsung-Yung Chang
  • Memory device
    Patent number: 11264109
    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chien-Yin Liu, Yi-Chun Shih
  • Segmented reference trimming for memory arrays
    Patent number: 11250908
    Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Der Chih, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Ku-Feng Lin
  • MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME
    Publication number: 20220035981
    Abstract: A memory cell array includes a first and a second column of memory cells, a first and a second bit line, a source line and a first set of vias. The first or second bit line includes a first conductive line located on a first metal layer, and a second conductive line located on a second metal layer. The first and second conductive lines overlap a source of a transistor of a memory cell of the first column or second column of memory cells. The source line is coupled to the first and second column of memory cells. The first set of vias is electrically coupled to the first and second conductive line. A pair of vias of the first set of vias is located above where the first conductive line overlaps each memory cell of the first or second column of memory cells.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Inventors: Chi-Hsiang WENG, Yu-Der CHIH
  • Resistive random access memory device
    Patent number: 11232836
    Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Fu Lee, Yu-Der Chih
  • IN-MEMORY COMPUTATION CIRCUIT AND METHOD
    Publication number: 20220019407
    Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
    Type: Application
    Filed: March 16, 2021
    Publication date: January 20, 2022
    Inventors: Yu-Der CHIH, Hidehiro FUJIWARA, Yi-Chun SHIH, Po-Hao LEE, Yen-Huei CHEN, Chia-Fu LEE, Jonathan Tsung-Yung CHANG
  • Memory sense amplifier trimming
    Patent number: 11227640
    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Shih, Chia-Fu Lee, Yu-Der Chih