Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To mitigate some risk associated with heating, the data processing system may proactively calibrate temperature sensors used to guide the heating process.

Abstract: Disclosed are a headphone and an operating method thereof. The headphone includes a headband frame, a speaker module, a detector and a controller. The speaker module is disposed on the headband frame. The detector is disposed in the headband frame and detect stress changes on the headband frame to output a frequency response voltage value. The controller is electrically connected to the speaker module and the detector, and receives the frequency response voltage value. The controller determines whether the frequency response voltage value is the same as a target frequency response voltage value to read a target frequency response parameter corresponding to the target frequency response voltage value. The controller drives the speaker module according to the target frequency response parameter.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

Abstract: A high-speed connector includes an insulating housing, a first terminal assembly received in the insulating housing, a second terminal assembly received in the insulating housing, a third terminal assembly received in the insulating housing, and a fourth terminal assembly received in the insulating housing. The second terminal assembly is opposite to the first terminal assembly along an up-down direction. The third terminal assembly is disposed between the first terminal assembly and the second terminal assembly. The fourth terminal assembly is corresponding to the third terminal assembly. The fourth terminal assembly is disposed between the second terminal assembly and the third terminal assembly.

Abstract: A composition is provided, wherein the composition includes 70.00-99.00 weight percentage (wt %) of phytopeptide, 0.10-20.00 wt % of branched-chain amino acid, 0.10-20.00 wt % of whey protein concentrate, 0.10-20.00 wt % of creatine, and 0.10-20.00 wt % of chromium yeast. A use of composition as described above is further provided.

Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: A high-speed connector includes an insulating housing, and at least one terminal assembly disposed in the insulating housing. The at least one terminal assembly includes a base body, a plurality of terminals fastened to the base body, and a metal block. A surface of the base body is recessed inward to form a fastening groove. The plurality of the terminals include a plurality of grounding terminals and differential signal terminals. Each of the plurality of the grounding terminals and the differential signal terminals has a fastening portion. The fastening portions of at least several of the plurality of the grounding terminals and the differential signal terminals are exposed to the fastening groove. The metal block is fastened in the fastening groove. The fastening portions of the grounding terminals which are exposed to the fastening groove are electrically connected with the metal block to form a grounding structure.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

Abstract: A dual lens inspection device, having a low power lens group satisfies the condition value of 3.0?magnification?1.0; a high power lens group, satisfies the condition value of 25.0?magnification?15.0; a light source module projecting an illumination light source to the low power lens group and the high power lens group; a beam splitter arranged on the optical path of the illumination light source, so as to generate a first optical path passing through the low power lens group and a second optical path passing through the high power lens group, and projected on an object located on the same plane; a first luminous flux module and a second luminous flux module control the luminous flux of the first and second optical path, and then achieve the effect of dark field illumination; a camera using the beam splitter to achieve a beam steering effect, and then captures the image of the object.

Abstract: Provided are a memory device and a pre-charge method for a memory device. The pre-charge method includes: applying a plurality of independently-controlled pre-charge voltages to a plurality of turned-on word lines, wherein the plurality of pre-charge voltages are selected among a plurality of reference pre-charge voltages; and applying a plurality of turned-off voltages to a plurality of turned-off word lines. On a predetermined direction, a target turned-on word line among the plurality of turned-on word lines is adjacent to a next adjacent target turned-off word line among the plurality of turned-off word lines; and a voltage difference from the target turned-on word line toward the next adjacent target turned-off word line is smaller than a predetermined reference voltage difference.

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

Abstract: A wrist-wearable electronic device comprising a house, a display, and a lens module. The lens module is coupled to a sidewall of the housing and can include a first light emitting element, a lens, and a first Frensel structure. The lens includes a body, a lower surface, and an upper surface. The first Frensel structure is disposed on the lower surface of the lens and is configured to disperse light generated by the first light emitting element into the body of the lens.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.