Abstract: An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.

Abstract: A package structure and method for forming the same are provided. The package structure includes a top interposer formed over a substrate, and a first die formed over the top interposer. The first die includes an optical package structure, and the optical package structure includes first optical components. The first die also includes an electronic die bonded to the optical package structure to form a hybrid bonding structure. The hybrid bonding structure includes a metal-to-metal bonding and dielectric-to-dielectric bonding. The package structure includes an optical die adjacent to the first die, and the top interposer is shared by the optical die and the first die.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a transistor, and a capacitor structure. The transistor includes a gate electrode material. The capacitor structure includes a first electrode and a second electrode including the gate electrode material. The capacitor structure also includes a plurality of first conductive features disposed over the first electrode and a plurality of conductive vias disposed over a corresponding one of the plurality of first conductive features. The capacitor structure further includes a third electrode over the plurality of conductive vias and electrically connected to the first electrode through the plurality of first conductive features and the plurality of conductive vias.

Abstract: An electrical connector includes an insulating housing, an upper terminal assembly fastened in the insulating housing, a center grounding plate fastened in the insulating housing, and an outer shell disposed to a top surface of the insulating housing. A rear end of the insulating housing has two first penetrating grooves. The upper terminal assembly includes an upper base portion. A rear end of the upper base portion defines two second penetrating grooves. The two second penetrating grooves are aligned with the two first penetrating grooves. Two opposite sides of a rear end of a top surface of the outer shell extend towards the insulating housing to form two elastic arms, respectively. The two elastic arms pass through the two first penetrating grooves and the two second penetrating grooves, and then the two elastic arms contact with two outermost upper grounding terminals of the upper terminal assembly.

Abstract: A magnetic door lock includes a door lock kit and a door frame lock kit. The door lock kit includes a deadbolt having a retaining slidable sleeve disposed in a deadbolt guiding slot in a housing, and a magnet disposed in the sleeve. The deadbolt is operable to slide between a locking position, where a retaining end of the sleeve projects outwardly from the housing, and an unlocking position, where the retaining end retreats into the slot. A driving member is operable to drive the deadbolt to slide from the locking position to the unlocking position. The door frame lock kit includes a lock frame and a magnet which is magnetically attracted to the magnet to urge the deadbolt to slide into the lock frame in the locking position.

Abstract: A control system for an electronic lock includes a control module. The electronic lock has a locked state and an unlocked state. The control module is configured to communicate with a portable device for receiving an unlock request 5 that includes a digital signature and a request identifier therefrom. The control module includes a processing unit and a storage electrically connected to the processing unit. The storage stores a key and a registered identifier. The processing unit is configured to, in response to receipt of the unlock request, verify the digital signature using the key, in response to successfully verifying the digital 10 signature, determine whether the request identifier matches the registered identifier, and in response to determining that the request identifier matches the registered identifier, control the electronic lock to switch from the locked state to the unlocked state.

Abstract: Semiconductor-on-insulator (SOI) structures with variable resistivity epitaxial semiconductor layers and methods of making the same are disclosed. The SOI structures may include customized resistivity profiles without changing the epitaxial structure of vendor-supplied base materials or requiring the development of new etching chemistries. An SOI structure may be formed by forming a second epitaxial semiconductor layer over a first epitaxial semiconductor layer on a first substrate, where the resistivity of the second epitaxial semiconductor layer is different than the resistivity of the first epitaxial semiconductor layer, forming a dielectric capping layer over the second epitaxial semiconductor layer, bonding the dielectric capping layer to a second dielectric capping layer on a second substrate, and removing the first substrate to provide the SOI structure. An optional third epitaxial semiconductor layer may be formed over the first epitaxial semiconductor layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.

Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

Abstract: A micro device mass transfer equipment including a base stage, a moving stage, a substrate stage, a laser device, a rolling and pressing mechanism, and a heating mechanism is provided. The moving stage is movably disposed on the base stage, and moves with a moving path. The substrate stage is movably disposed on the base stage, and is adapted to move between different positions overlapping the moving stage. The laser device is movably disposed on the base stage. The laser device is adapted to move relative to the substrate stage, and emits a laser beam toward the substrate stage. The rolling and pressing mechanism is disposed on the moving path of the moving stage, and forms a contact region with the moving stage. The heating mechanism is disposed corresponding to the contact region, and is adapted to heat the contact region between the moving stage and the rolling and pressing mechanism.

Abstract: A method and a system for setting a digital equalizer are provided. The method and the system are applicable to a signal receiver. The signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, and the target digital equalizer has an equalizer coefficient. The method includes: obtaining, during a simulation phase, a plurality of coefficient initial values and a plurality of coefficient limit values that respectively correspond to a plurality of preset transmission channels; and setting, during a connection phase, the equalizer coefficient of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels.

Abstract: In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: The application provides a method for creating a usage scenario determination database and a mobile communication system for the same. In creating a first part of the usage scenario determination database, an impedance of at least one first tuner is repeatedly measured until all antennas among the antenna group are selected, a plurality of predetermined testing frequencies are selected and a plurality of tuning states of the at least one first tuner are selected. In creating a second part of the usage scenario determination database, an antenna impedance is repeatedly measured until all antennas among the antenna group are selected, the plurality of predetermined testing frequencies are selected, a plurality of tuning states of at least one second tuner are selected and at least one usage scenario is selected. The usage scenario determination database is created base on the first part and the second part.

Abstract: A micro LED display device includes a display substrate. The display substrate has a first transfer area and a second transfer area adjacent to each other. Both the first transfer area and the second transfer area include a plurality of pixel areas. The pixel area of the first transfer area includes a first micro light-emitting element arranged in a straight line along a first direction. The pixel area of the second transfer area includes a second micro light-emitting element arranged in another straight line along the first direction. In the first direction, the first micro light-emitting element and the second micro light-emitting element are arranged in a staggered manner. A manufacturing method of a micro LED display device is also provided.

Abstract: A plug electrical connector and an electrical connector combination having the same are disclosed. The plug electrical connector includes a plug insulation structure; a plurality of plug terminals joined to the plug insulation structure; a movable member movably disposed on the plug insulation structure; at least one contact terminal joined to the movable member; wherein the at least one contact terminal and the movable member move simultaneously between a contact position and a retreat position. The electrical connector combination includes the aforementioned plug electrical connector and a receptacle electrical connector. The receptacle electrical connector includes a receptacle insulation structure; a plurality of receptacle terminals joined to the receptacle insulation structure; at least one detecting terminal joined to the receptacle insulation structure. The contact terminal is selectively to contact the detecting terminal, whereby certain specific functions of an electronic device are activated.

Abstract: A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.

Abstract: A semiconductor device and method of manufacturing are disclosed. The semiconductor device includes an optical die, a laser die, and an interposer. The optical die has photonic integrated circuits (PICs), electronic integrated circuits (EICs), and one or more first coupling waveguides. The laser die has at least one laser diode and one or more second coupling waveguides. The optical die and the laser die are bonded to a first side of the interposer using a metal-to-metal bonding, where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides. An optical glue fills a gap between the aligned at least one of the one or more first coupling waveguides and the at least one of the one or more second coupling waveguides.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.