Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A light-emitting device includes an epitaxial structure having a first surface and a second surface that is opposite to the first surface. The epitaxial structure includes, along a first direction from the first surface to the surface, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer including a capping layer. The capping layer includes at least Ni number of sub-layers arranged in the first direction, where N1?2. Each of the sub-layers of the capping layer contains a material represented by Aly1Ga1-y1InP, where 0<y1?1. The capping layer has an Al content which increases and then remains constant along the first direction. A light-emitting apparatus includes the light-emitting device is also provided.

Abstract: A multi junction solar cell structure includes a first sub-cell, a first tunnel diode layer, a second tunnel diode layer, a second sub-cell, a lattice gradient buffer layer and a third sub-cell. The first sub-cell includes a first surface and a second surface opposite to the first surface. The first tunnel diode layer is formed on the first surface of the first sub-cell. The second sub-cell is formed on the first tunnel diode layer. The second tunnel diode layer is formed on the second surface of the first sub-cell. The lattice gradient buffer layer is formed on the second tunnel diode. The third sub-cell is formed on the lattice gradient buffer layer. This disclosure also contains a method for manufacturing the above-mentioned multi-junction solar cell.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: A semiconductor device includes a single-layered dielectric layer, a conductive line, a conductive via and a conductive pad. The conductive line and the conductive via are disposed in the single-layered dielectric layer. The conductive pad is extended into the single-layered dielectric layer to electrically connected to the conductive line.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To mitigate some risk associated with heating, the data processing system may proactively calibrate temperature sensors used to guide the heating process.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A display device and a projector are provided. The display device includes a pixel light-emitting panel and multiple color conversion panels. The pixel light-emitting panel includes an N1 number of light-emitting pixel units distributed in an array, and the light-emitting pixel units are driven to emit light through a driver. A first color conversion panel includes an N2 number of first color pixels and an N3 number of first transparent pixels. The first color pixels and the first transparent pixels are disposed relative to the light-emitting pixel units. A second color conversion panel includes an N4 number of second color pixels and an N5 number of second transparent pixels. The second color pixels and the second transparent pixels are disposed relative to the light-emitting pixel units. The lights generated by at least part of the light-emitting pixel units sequentially pass through the first color pixels and the second transparent pixels to achieve the color conversion.

Abstract: A light-emitting device is provided. The light-emitting device includes a light-emitting unit and a light-conversion structure disposed on the light-emitting unit, wherein the light-conversion structure includes a quantum dot layer and an etching blocking layer disposed on one of the surfaces of the quantum dot layer.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.

Abstract: A terminal device and a terminal device installation method are provided. The terminal device includes a machine body, a detachable cover with two side walls, and at least two coupling mechanisms arranged symmetrically. The machine body includes a front board, a rear board opposite to the front board, and two side boards connected between the front board and the rear board. Each coupling mechanism includes a coupling portion located at one side wall, a front track and a rear track respectively having a front opening and a rear opening opposite to the front opening and both located at one side board. As each coupling portion is coupled to each front track, the cover is assembled with the machine body and covers the front board, and as each coupling portion is coupled with each rear track, the cover is assembled to the machine body and covers the rear board.

Abstract: A mending method for a display includes the steps of making a display device light to make a plurality of light emitting positions thereof shine, searching out a plurality of defect positions among the light emitting positions, providing a transferring device having a transferring surface with a plurality of miniature light emitting elements positioned correspondingly to the light emitting positions, planning a mending procedure which includes in the area the transferring surface corresponds to, choosing in chief the largest number of defect positions able to be mended at a single time according to the positions of the miniature light emitting elements and then in the area the transferring surface corresponds to, planning the rest of the defect positions according to the rest of the miniature light emitting elements, and according to the mending procedure, moving the transferring device to weld the miniature light emitting elements at the defect positions.

Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.