Patents by Inventor Yu Hung

Yu Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20240175649
    Abstract: A heat exchange tube is used to solve the problem of insufficient heat exchange efficiency of the conventional heat exchange tube. The heat exchange tube includes a tube, a first porous layer, and a second porous layer. The tube includes an inner wall. The first porous layer includes a plurality of holes. The first porous layer is disposed on the inner wall of the tube. The second porous layer includes a plurality of holes. The second porous layer is disposed on an inner surface of the first porous layer. An average diameter of the plurality of holes of the second porous layer is greater than an average diameter of the plurality of holes of the first porous layer. A method for manufacturing a heat exchange tube is also disclosed.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventors: Yu-Lin CHUNG, Chia-Hung HUANG, Jiun-Cherng LIU, Chi-Huei CHEN
  • Publication number: 20240177833
    Abstract: Provided are systems, methods, and computer program products for segmenting an image. A method includes segmenting each image in a sequence of images including a needle into a needle and at least one needle artifact based on processing each image with a first machine-learning model trained with a plurality of hard labels for a plurality of images, resulting in a plurality of hard-labeled images, transforming each hard-labeled image of the plurality of hard-labeled images into a soft-labeled image including pixel values corresponding to an effect of the at least one needle artifact, resulting in a plurality of soft-labeled images, and segmenting at least one image of the sequence of images based on processing the at least one image with a second machine-learning model trained at least partially with the plurality of soft-labeled images.
    Type: Application
    Filed: March 28, 2022
    Publication date: May 30, 2024
    Inventors: John Michael Galeotti, Ling Yu Hung
  • Publication number: 20240178328
    Abstract: Embodiments include a Schottky barrier diode (SBD) structure and method of forming the same, the SBD structure including a current blockage feature to inhibit current from leaking at an interface with a shallow trench isolation regions surrounding an anode region of the SBD structure.
    Type: Application
    Filed: May 1, 2023
    Publication date: May 30, 2024
    Inventors: Cheng-Hsien Wu, Chien-Lin Tseng, Sheng Yu Lin, Ting-Chang Chang, Yung-Fang Tan, Yu-Fa Tu, Wei-Chun Hung
  • Publication number: 20240176335
    Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Yung-Yu Yang, Kang-Ping Li, Chih-Kuan Chang, Chung-Chih Hung, Chen-Hui Huang, Nai-Ying Lo, Shih-Wei Huang
  • Publication number: 20240177503
    Abstract: The present invention discloses a port district sea line multiple vessel monitoring system and operating method thereof. Specifically, the port district sea line multiple vessel monitoring system comprises a processing module, a storage module, a camera and a floating object information receiving module. The port district sea line multiple vessel monitoring system may automatically recognize image classification of water surface object, therefore to determine operation of patrol mode, monitor mode or auxiliary recognizing mode for satisfying the needs of monitoring of port district sea line.
    Type: Application
    Filed: November 25, 2023
    Publication date: May 30, 2024
    Inventors: YU-TING PENG, YAN-SHENG SONG, CHIA-YU WU, CHIEN-HUNG LIU
  • Publication number: 20240178264
    Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Chun-Wei HSU, Tsai-Hao HUNG, Chung-Yu LIN, Ying-Hsun CHEN
  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Patent number: 11996058
    Abstract: A display device is provided and includes a display panel, a light source, a light source controller, and a timing controller. The light source is adjacent to the display panel. The light source controller is electrically connected to the light source. The timing controller is electrically connected to the light source controller and the display panel. The timing controller includes a decoding unit and first and second processing units. The first processing unit is electrically connected to the decoding unit and the display panel. The second processing unit is electrically connected to the decoding unit and the light source controller. The decoding unit provides a refresh signal to the first and second processing units so that the display panel refreshes displayed content in a first refresh sequence according to first refresh rates, and the light source refreshes brightness in a second refresh sequence according to second refresh rates.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 28, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Huang-Chi Chao, Wei-Cheng Tsai, Ming-Chi Weng, Yu-Hsin Feng, Cheng-Tso Hsiao, Ming-Feng Hsieh, Chien-Hung Chan
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Publication number: 20240170896
    Abstract: A composite mounting type electrical connector includes an insulating shell, a plurality of terminals and a plurality of shielding members. The plurality of terminals are arranged in two rows parallel to each other, and a plurality of shielding members are arranged between the two rows of terminals and separated from each other by a predetermined distance to form insulation. The two rows of terminals are soldered to a circuit board by surface mounting technology and dual in line package process respectively. The ground terminals in the two columns of terminals are commonly connected to a shield spacer to form a common ground structure. The power terminals in the two columns of terminals are commonly connected to another shielding member to form a parallel connecting structure. The shielding members produce a shielding effect between two rows of terminals, which can prevent crosstalk therebetween.
    Type: Application
    Filed: May 27, 2023
    Publication date: May 23, 2024
    Inventors: MING LUO, YUNG- CHANG LIN, YU-HUNG LIN, HUNG-TIEN CHANG, HSUAN HO CHUNG
  • Publication number: 20240170473
    Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.
    Type: Application
    Filed: July 6, 2023
    Publication date: May 23, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Hao-Che Kao, Wen-Hung Liu, Yu-Min Lin, Ching-Kuan Lee
  • Publication number: 20240170789
    Abstract: A system includes a first group of cells having a first battery chemistry type and a second group of cells having a second battery chemistry type. Cells from the first group of cells and cells from the second group of cells are arranged in an alternating manner in a first direction of a battery pack that includes the first group of cells and the second group of cells.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 23, 2024
    Inventors: Yu-Hung Li, Edward T. Hillstrom
  • Patent number: 11988972
    Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsun Lin, Yu-Hsiang Ho, Jhun Hua Chen, Chi-Hung Liao, Teng Kuei Chuang
  • Patent number: 11990906
    Abstract: Disclosed is an electronic device including a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element during a first time period. The second power supply circuit drives the tunable element during a second time period.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: May 21, 2024
    Assignee: Innolux Corporation
    Inventors: Yi-Hung Lin, Chung-Le Chen, Shuo-Ting Hong, Yu-Ti Huang, Yu-Hsiang Chiu, Nai-Fang Hsu
  • Patent number: 11990836
    Abstract: A power supply system with dynamic current sharing includes a current-sharing bus and a plurality of power supply units connected to each other through the current-sharing bus. The current-sharing bus provides a first current signal. Each power supply unit includes a local current bus for providing a second current signal. The active current-sharing unit compares the first current signal with the second current signal to generate a compensation voltage. The current-averaging unit compares a difference value between an average value of the first current signal and an average value of the second current signal to generate an average voltage. The droop current unit receives the second current signal to generate a droop compensation voltage. The integration calculation unit makes output currents of the power supply units be approximately equal according to the compensation voltage, the average voltage, and the droop compensation voltage.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: May 21, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Hung Lin, Guo-Hua Wang, Yu-Jie Lin, Hsien-Kai Wang
  • Patent number: 11990507
    Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20240162071
    Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Chih-Hung HUANG, Cheng-Lung WU, Yi-Fam SHIU, Yu-Chen CHEN, Yang-Ann CHU, Jiun-Rong PAI
  • Publication number: 20240162372
    Abstract: A light-emitting device includes a semiconductor epitaxial structure that has a first surface and a second surface opposite to the first surface, and that includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed in such order in a direction from the first surface to the second surface. The active layer includes well layers and barrier layers that are alternately stacked. The active layer has an upper surface that is adjacent to the second semiconductor layer, and a lower surface that is opposite to the upper surface. The first semiconductor layer is doped with an n-type dopant, which has a first concentration of 5E17/cm3 at a first point in the first semiconductor layer. The first point of the first semiconductor layer and the lower surface of the active layer have a first distance therebetween. The first distance ranges from 150 nm to 500 nm.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: Weihuan LI, Jinghua CHEN, Huan-Shao KUO, Yu-Ren PENG, Dongpo CHEN, Chia-Hung CHANG
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung