Abstract: A dual lens inspection device, having a low power lens group satisfies the condition value of 3.0?magnification?1.0; a high power lens group, satisfies the condition value of 25.0?magnification?15.0; a light source module projecting an illumination light source to the low power lens group and the high power lens group; a beam splitter arranged on the optical path of the illumination light source, so as to generate a first optical path passing through the low power lens group and a second optical path passing through the high power lens group, and projected on an object located on the same plane; a first luminous flux module and a second luminous flux module control the luminous flux of the first and second optical path, and then achieve the effect of dark field illumination; a camera using the beam splitter to achieve a beam steering effect, and then captures the image of the object.

Abstract: A hollow pipe cooling device includes a covering member, a spacer member and a hollow pipe. A top surface of the spacer member is partially exposed to a top cover opening of the covering member. The hollow pipe includes a surrounding wall part and a closed end part. A first end of the surrounding wall part is connected with the closed end part. A second end of the surrounding wall part is an opened end part. A heat dissipation space is defined by the surrounding wall part and the closed end part collaboratively. The opened end part is used as an entrance/exit of the heat dissipation space. A hollow pipe wick structure is formed on an inner wall of the surrounding wall part. The opened end part is aligned with the corresponding top cover opening and contacted with the spacer member.

Abstract: A structure for protecting an electronic component from coolant leaking from a liquid cooling system is disclosed. The liquid cooling system has a manifold collecting and supplying coolant to a cold plate via inlet and outlet tubes. The cold plate is mounted over a heat-generating component on a circuit board. The structure includes a drip tray having a top surface and a length approximately the distance between the manifold and the cold plate. The drip tray includes a trough for collection of leaking coolant. The tray is inserted between the circuit board and the inlet and outlet tubes.

Abstract: A device state evaluation method based on current signals is applied to a target device that is powered on, the device state evaluation method includes: collecting a plurality of target current signals corresponding to the target device via an acquisition module; performing a signature extraction operation and a normalization operation via a computing module to obtain a target matrix by using the plurality of target current signals; and performing a diagnosis operation on the target matrix via a diagnosis module to identify whether the target device is in a malfunction state, where an identification result of the diagnosis operation is used as target information. Therefore, whether the target device is in the malfunction state can be evaluated by analyzing the plurality of target current signals. A device state evaluation system is also provided.

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit including a main transistor, a resistor element and a control circuit. A first voltage terminal is coupled to a second terminal of the main transistor and a first terminal of the resistor element. A second voltage terminal is coupled to a first terminal of the main transistor. The control circuit is coupled between a second terminal of the resistor element and a control terminal of the main transistor. When an ESD event occurs, the product of the capacitance value of a parasitic capacitance of the control circuit and the resistance value of the resistor element is greater than the duration of the ESD event, and the control circuit turns on the main transistor so that an ESD current flows through the main transistor.

Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

Abstract: A transistor stack circuit including a first signal transmission port, a second signal transmission port, an impedance unit, a plurality of transistors, and a plurality of resistors is provided. The transistors are connected in series and coupled between the first signal transmission port and the second signal transmission port. A first terminal of each resistor is coupled to a common path. A second terminal of each resistor is coupled to a control terminal of a corresponding transistor among the transistors. The impedance unit is coupled between the common path and a reference voltage terminal. When an electrostatic discharge event occurs, an impedance value of the impedance unit is greater than twice of a resistance value of each resistor, and the transistors form a low-impedance path.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: A sensing rack includes a base, a plurality of sensing mechanisms, and a plurality of displaying elements. The base includes a plurality of accommodating spaces. The sensing mechanisms are disposed in the base, and each of the sensing mechanisms correspond to each of the accommodating spaces and includes a light sensing component and a light blocking element. A light sensing component includes a light emitting element and a light receiving element. The light blocking element is drivable to move between the light emitting element and the light receiving element so as to control a light of the light emitting element to enter the light receiving element or not. Each of the displaying elements is electrically connected with the light receiving element of each of the sensing mechanisms and is for displaying the light of each of the light emitting elements entering the light receiving element or not.

Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.

Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.

Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may heat them when their temperatures fall outside of thermal operating ranges. To mitigate some risk associated with heating, the data processing system may proactively calibrate temperature sensors used to guide the heating process.

Abstract: Disclosed are a headphone and an operating method thereof. The headphone includes a headband frame, a speaker module, a detector and a controller. The speaker module is disposed on the headband frame. The detector is disposed in the headband frame and detect stress changes on the headband frame to output a frequency response voltage value. The controller is electrically connected to the speaker module and the detector, and receives the frequency response voltage value. The controller determines whether the frequency response voltage value is the same as a target frequency response voltage value to read a target frequency response parameter corresponding to the target frequency response voltage value. The controller drives the speaker module according to the target frequency response parameter.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

Abstract: A high-speed connector includes an insulating housing, a first terminal assembly received in the insulating housing, a second terminal assembly received in the insulating housing, a third terminal assembly received in the insulating housing, and a fourth terminal assembly received in the insulating housing. The second terminal assembly is opposite to the first terminal assembly along an up-down direction. The third terminal assembly is disposed between the first terminal assembly and the second terminal assembly. The fourth terminal assembly is corresponding to the third terminal assembly. The fourth terminal assembly is disposed between the second terminal assembly and the third terminal assembly.

Abstract: A composition is provided, wherein the composition includes 70.00-99.00 weight percentage (wt %) of phytopeptide, 0.10-20.00 wt % of branched-chain amino acid, 0.10-20.00 wt % of whey protein concentrate, 0.10-20.00 wt % of creatine, and 0.10-20.00 wt % of chromium yeast. A use of composition as described above is further provided.

Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.

Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Abstract: A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.