Patents by Inventor Yu-Hung Lin

Yu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253298
    Abstract: A package structure and method for forming the same are provided. The package structure includes a top interposer formed over a substrate, and a first die formed over the top interposer. The first die includes an optical package structure, and the optical package structure includes first optical components. The first die also includes an electronic die bonded to the optical package structure to form a hybrid bonding structure. The hybrid bonding structure includes a metal-to-metal bonding and dielectric-to-dielectric bonding. The package structure includes an optical die adjacent to the first die, and the top interposer is shared by the optical die and the first die.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 7, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua YU, Hsing-Kuo HSIA, Ren-Fen TSUI, Yu-Hung LIN, Jui-Lin CHAO
  • Patent number: 12374596
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai
  • Patent number: 12374602
    Abstract: A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: July 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Yu-Hsiao Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Patent number: 12368280
    Abstract: In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: July 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Chia-Nan Yuan, Shih-Guo Shen, Der-Chyang Yeh, Yu-Hung Lin, Ming Shih Yeh
  • Publication number: 20250226621
    Abstract: A plug electrical connector and an electrical connector combination having the same are disclosed. The plug electrical connector includes a plug insulation structure; a plurality of plug terminals joined to the plug insulation structure; a movable member movably disposed on the plug insulation structure; at least one contact terminal joined to the movable member; wherein the at least one contact terminal and the movable member move simultaneously between a contact position and a retreat position. The electrical connector combination includes the aforementioned plug electrical connector and a receptacle electrical connector. The receptacle electrical connector includes a receptacle insulation structure; a plurality of receptacle terminals joined to the receptacle insulation structure; at least one detecting terminal joined to the receptacle insulation structure. The contact terminal is selectively to contact the detecting terminal, whereby certain specific functions of an electronic device are activated.
    Type: Application
    Filed: December 16, 2024
    Publication date: July 10, 2025
    Inventors: MING LUO, YUNG- CHANG LIN, YU-HUNG LIN, HUNG-TIEN CHANG, HSUAN HO CHUNG
  • Publication number: 20250216600
    Abstract: A semiconductor device and method of manufacturing are disclosed. The semiconductor device includes an optical die, a laser die, and an interposer. The optical die has photonic integrated circuits (PICs), electronic integrated circuits (EICs), and one or more first coupling waveguides. The laser die has at least one laser diode and one or more second coupling waveguides. The optical die and the laser die are bonded to a first side of the interposer using a metal-to-metal bonding, where at least one of the one or more first coupling waveguides is optically aligned with at least one of the one or more second coupling waveguides. An optical glue fills a gap between the aligned at least one of the one or more first coupling waveguides and the at least one of the one or more second coupling waveguides.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Yu-Hung Lin, Ren-Fen Tsui, Kuo-Chung Yee, Chen-Hua Yu
  • Patent number: 12341104
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.
    Type: Grant
    Filed: February 14, 2024
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
  • Publication number: 20250164690
    Abstract: Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.
    Type: Application
    Filed: March 1, 2024
    Publication date: May 22, 2025
    Inventors: Yu-Hung Lin, Yu-Hao Kuo, Chih-Hao Yu, Ren-Fen Tsui, Jui Lin Chao, Hsing-Kuo Hsia, Kuo-Chung Yee, Chen-Hua Yu
  • Patent number: 12298226
    Abstract: A sensing rack includes a base, a plurality of sensing mechanisms, and a plurality of displaying elements. The base includes a plurality of accommodating spaces. The sensing mechanisms are disposed in the base, and each of the sensing mechanisms correspond to each of the accommodating spaces and includes a light sensing component and a light blocking element. A light sensing component includes a light emitting element and a light receiving element. The light blocking element is drivable to move between the light emitting element and the light receiving element so as to control a light of the light emitting element to enter the light receiving element or not. Each of the displaying elements is electrically connected with the light receiving element of each of the sensing mechanisms and is for displaying the light of each of the light emitting elements entering the light receiving element or not.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: May 13, 2025
    Assignee: RHYMEBUS CORPORATION
    Inventors: Hsuan-Yu Huang, Chiu-Hsiung Chen, Shun-Han Ko, Yu-Hung Lin, Hsien-Tang Jao
  • Publication number: 20250151381
    Abstract: The present disclosure describes a semiconductor device having fin structures with optimized fin pitches for substantially uniform S/D structures. The semiconductor device includes multiple fin structures on a substrate. The multiple fin structures have a first pitch and a second pitch in an alternate configuration and the second pitch is different from the first pitch. The semiconductor device further includes a gate structure on the multiple fin structures and a source/drain (S/D) structure adjacent to the gate structure and in contact with the multiple fin structures.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung LIN, Wei Hsin LIN, Hui-Hsuan KUNG, Yi-Lii HUANG
  • Publication number: 20250149477
    Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Yu-Hung Lin, Chih-Hao Yu, Wei-Ming Wang, Chen Chen, Chia-Hui Lin, Ren-Fen Tsui, Chen-Hua Yu
  • Publication number: 20250118612
    Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen Chen, Yu-Hung Lin, Chih-Hao Yu, Wei-Ming Wang, Chia-Hui Lin, Shih-Peng Tai
  • Patent number: 12272613
    Abstract: A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Yu-Hung Lin, Shih-Peng Tai, Kuo-Chung Yee
  • Publication number: 20250052966
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yi HUANG, Yu-Hao KUO, Chiao-Chun CHANG, Jui-Hsuan TSAI, Yu-Hung LIN, Shih-Peng TAI, Jih-Churng TWU, Chen-Hua YU
  • Publication number: 20250031434
    Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.
    Type: Application
    Filed: July 17, 2023
    Publication date: January 23, 2025
    Inventors: Yu-Hung Lin, Jih-Churng Twu, Su-Chun Yang, Shih-Peng Tai, Yu-Hao Kuo
  • Patent number: 12203646
    Abstract: A wrist-wearable electronic device comprising a house, a display, and a lens module. The lens module is coupled to a sidewall of the housing and can include a first light emitting element, a lens, and a first Frensel structure. The lens includes a body, a lower surface, and an upper surface. The first Frensel structure is disposed on the lower surface of the lens and is configured to disperse light generated by the first light emitting element into the body of the lens.
    Type: Grant
    Filed: May 28, 2024
    Date of Patent: January 21, 2025
    Assignee: Garmin International, Inc.
    Inventors: Cheng-Yu Tsai, Minhung Lee, Yu-Hung Lin, Yung-Lang Yang
  • Publication number: 20240404909
    Abstract: A method for forming a package structure is provided, wherein the method includes forming an interconnect structure in a substrate. The method also includes bonding a chip over the substrate and electrically connected to the interconnect structure. The method includes bonding a plurality of dies over the substrate and adjacent to the chip. The method also includes supplying a molding material to the gap between the chip and the dies, after which the method includes thinning down the substrate.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Yu-Hung LIN, Shih-Peng TAI, Yu-Yi HUANG, Yu-Hao KUO
  • Publication number: 20240377972
    Abstract: A read voltage calibration method, a memory storage device, a memory control circuit unit are provided, including: reading, according to a first read command, a first physical unit based on a first read voltage level to obtain first data, and the first read voltage level is a default read voltage level corresponding to the first physical unit or a first voltage difference exists between the first read voltage level and the default read voltage level; decoding the first data to obtain first error bit information; reading, according to a second read command, the first physical unit based on a second read voltage level to obtain second data, and a second voltage difference exists between the second read voltage level and the default read voltage level; decoding the second data to obtain second error bit information; calibrating the default read voltage level according to the first and second error bit information.
    Type: Application
    Filed: June 16, 2023
    Publication date: November 14, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Szu-Wei Chen, Yu-Hung Lin, I-Sung Huang, Po-Cheng Su
  • Patent number: 12112808
    Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: October 8, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Szu-Wei Chen, An-Cin Li, Yu-Hung Lin, Kai-Wei Tsou
  • Publication number: 20240332202
    Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Chih-Wei Wu, Chia-Nan Yuan, Ying-Ching Shih, An-Jhih Su, Szu-Wei Lu, Ming-Shih Yeh, Der-Chyang Yeh