Abstract: The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

Abstract: A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Abstract: The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.

Abstract: An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

Abstract: An array controlling system includes a database, a controlling center and an array device. The controlling center reads a plurality of data of the database. The array device includes a processing unit, a main bus and an array unit. The processing unit receives a command of the controlling center and converts the command into a communication data. The main bus is configured to transmit the communication data to the array unit. A plurality of array modules of the array unit are connected in series with each other through a serial bus, and sequentially receive the communication data. The processing unit controls each of the array modules according to the communication data. A plurality of sensing data of the array modules are collected to the processing unit. The processing unit returns the sensing data to the database or the controlling center to update the database.

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.

Abstract: An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal.

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first conductor group and a second conductor group. The first conductor group includes a backup transmission conductor, first and second signal transmission conductors, an inspection signal transmission conductor, first to seventh grounding transmission conductors, a command reset transmission conductor, first to sixth differential transmission conductors, first and second power transmission conductors, and a write-protection transmission conductor, each of which has two ends respectively forming a spring section and a soldering section. The second conductor group includes eighth to tenth grounding transmission conductors, seventh to tenth differential transmission conductors, and a third power transmission conductor each of which has two ends respectively forming a spring section and a soldering section.

Abstract: A card connector includes a transmission conductor assembly that includes a backup transmission conductor, a first signal transmission conductor, an inspection signal transmission conductor, a first grounding transmission conductor, a command reset transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a fourth grounding transmission conductor, a first power transmission conductor, a second power transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a second signal transmission conductor, a fifth grounding transmission conductor, a sixth grounding transmission conductor, a seventh grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and a write-protection transmission conductor, each of which has two ends respectively forming a spring se

Abstract: A card connector includes a transmission conductor assembly. The transmission conductor assembly includes a first signal transmission conductor, a first power transmission conductor, an inspection signal transmission conductor, a second signal transmission conductor, a command reset transmission conductor, a first grounding transmission conductor, a second power transmission conductor, a first differential transmission conductor, a second differential transmission conductor, a third signal transmission conductor, a second grounding transmission conductor, a third grounding transmission conductor, a third differential transmission conductor, a fourth differential transmission conductor, a fourth grounding transmission conductor, a fifth grounding transmission conductor, a fifth differential transmission conductor, a sixth differential transmission conductor, and an outside grounding transmission conductor, each of which has a spring section and a soldering section.

Abstract: A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.