Patents by Inventor Yu-Hung Lin

Yu-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504778
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10483208
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20190279939
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20190252247
    Abstract: A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Ya-Lien LEE, Hung-Wen SU, Kuei-Pin LEE, Yu-Hung LIN, Yu-Min CHANG
  • Publication number: 20190252248
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Publication number: 20190221522
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Patent number: 10340218
    Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Patent number: 10297548
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Publication number: 20190149765
    Abstract: A cable connection element for reducing signal transmission loss includes a front clad, a base and a connection terminal. The connection terminal has a first core-holding portion formed on a front end thereof, a second core-holding portion formed on a rear end thereof, a core-clamping portion formed between the first and second core-holding portions, and a pin formed on a rear end of the second core-holding portion. The second core-holding portion is fixed inside the base. The front clad is connected with the base to enclose the first core-holding portion therein. When a core of a cable penetrates the front clad, the core is held by the core-clamping portion and is electrically connected therewith, such that signals from the core can be transmitted to the pin through the core-clamping portion and the second core-holding portion. Accordingly, signal transmission loss arising from capacitance effect can be improved.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 16, 2019
    Inventors: Jui-Huang CHUNG, Yu-Hung LIN
  • Patent number: 10276561
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes transferring the substrate from a stage to a deposition chamber, and no heating operation is performed on the stage. The method also includes depositing a resistor layer on the substrate. The resistor layer may have a major structure that is amorphous.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Tseng Chen, Hon-Lin Huang, Chun-Hsien Huang, Yu-Hung Lin
  • Patent number: 10276431
    Abstract: A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench; a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and a metal-containing layer formed over the PVD Ta layer.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Hung-Wen Su, Kuei-Pin Lee, Yu-Hung Lin, Yu-Min Chang
  • Patent number: 10276432
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10269630
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Patent number: 10269713
    Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
  • Patent number: 10263088
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20190109044
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 11, 2019
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 10170898
    Abstract: A signal leakage proof housing for signal distributors includes a metal case and a metal cover plate. The metal case includes a plurality of signal connection terminals and a circumferential side wall having a top surface. The top surface includes a plurality of fixing protrusions arranged at intervals on and around the top surface and at least one rib on and around the top surface. The metal cover plate includes a bottom surface which includes a plurality of fixing holes on and around the bottom surface. When the metal case and the metal cover plate are assembled together, the plurality of fixing protrusions respectively pass through the corresponding plurality of fixing holes and fix with each other and each one of the at least one rib is in direct contact with the bottom surface of the metal cover plate to achieve the objective of preventing electromagnetic signal leakage.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 1, 2019
    Assignee: Signal Cable System Co., Ltd.
    Inventors: Jui-Huang Chung, Yu-Hung Lin
  • Patent number: 10099269
    Abstract: A drawing device includes a main body, a seat body, a central axle, two supporting members and a driving structure. The seat body is rotatably connected to the main body and has two legs which have a preset distance therebetween, the central axle vertically penetrates the main body and the seat body and movable along a vertical direction, the main body and the seat body are rotatable about the central axle relative to each other, a bottom portion of the central axle penetrates the seat body for a sucking disc to be arranged thereon, the two supporting members are respectively swingably pivoted to the two legs of the seat body, and the central axle is located between the two supporting members, and the driving structure is attached to the main body and connected to the central axle to optionally move the central axle upward.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: October 16, 2018
    Inventors: Yu-Hung Lin, Cheng-Tse Chang
  • Publication number: 20180277429
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 27, 2018
    Inventors: Yu-Hung LIN, You-Hua CHOU, Sheng-Hsuan LIN, Chih-Wei CHANG
  • Patent number: 10079174
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu