Abstract: An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the interconnect structure, an ?-phase inducing metal layer is introduced on a first Ta barrier layer of ? phase to induce the subsequent deposition of Ta thereon into the formation of an ?-phase Ta barrier layer. The subsequently deposited Ta barrier layer with a primary crystallographic structure of ? phase has a lower Rc than that of the ?-phase Ta barrier layer.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate structure over a substrate and forming a spacer on a sidewall of the gate structure. The method for manufacturing a semiconductor structure further includes forming a hard mask structure on a top surface of the gate structure and on an upper portion of the spacer but not on a bottom portion of the spacer.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.

Abstract: Disclosed herein is a method of forming a metal-to-semiconductor contact with a doped metal oxide interlayer. An insulating layer is formed on a top surface of a semiconductor substrate with target region at the top surface of the semiconductor substrate. An opening is etched through the insulating layer with the opening exposing a top surface of a portion of the target region. A doped metal oxide interlayer is formed in the opening and contacts the top surface of the target region. The remainder of the opening is filled with a metal plug, the doped metal oxide interlayer disposed between the metal plug and the substrate. The doped metal oxide interlayer is formed from one of tin oxide, titanium oxide or zinc oxide and is doped with fluorine.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material.

Abstract: A method for producing a metal contact in a semiconductor device is disclosed. The method comprises depositing a catalyst layer in a via hole, forming a catalyst from the deposited catalyst layer, and growing a carbon nanotube structure above the catalyst in the via hole. The method further comprises forming salicide from the catalyst, applying a chemical mechanical polishing (CMP) process to the carbon nanotube structure to remove top layers of catalyst and nanotube material, and depositing metal material above the carbon nanotube structure. Growing a carbon nanotube structure comprises absorbing a precursor on a surface of the catalyst formed in the via hole, forming a metal-carbon alloy from the catalyst and the precursor, and growing a carbon nanotube structure vertically from the via bottom. The carbon nanotube structure comprises a plurality of carbon nanotubes wherein the diameters of the carbon nanotubes are limited by the catalyst size.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

Abstract: An electronic connector includes a transmission conductor group including two rows of plate-like contacts for insertion of a connector male portion in normal and reverse directions, a transmission conductor pin group, which is formed at a rear side of the transmission conductor group and arranged in a single row, a shielding housing, which receives therein the transmission conductor group, and an inclined cover section, which extends from the shielding housing to shield the transmission conductor pin group. As such, contacts of the transmission conductor group of the connector are provided in an arrangement of two rows so that mating between a male portion and a female portion can be made in a directionless manner, allowing for insertion in both normal and reverse directions. The transmission conductor pin group extending rearward from the transmission conductor group is set in an arrangement of a single row to maintain the convenience of manufacturing.

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

Abstract: A method includes etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening, and performing a bombardment to bombard a surface region of the underlying region through the opening. After the bombardment, the surface region is reacted with a process gas to form a reaction layer. An anneal is then performed to remove the reaction layer.

Abstract: A backup power supplying device having programmable current-balancing control includes at least two power modules connected in parallel. The power module includes a power converter, a current sensing component, a potential tuner, a microprocessor, a current-balancing control circuit and an output voltage controller. The current sensing component senses an output current of the power converter to generate a current sensing signal. The microprocessor controls the potential tuner to generate a tuning signal, and receives a mode signal to control the power module to operate in a power supply or sleep mode. The current-balancing control circuit receives the current sensing signal, the tuning signal and the mode signal. When the power module operates in the sleep mode, an output voltage of the power converter is a sleep voltage; a voltage level of the sleep voltage is lower than a voltage level of a supply voltage by a predetermined voltage value.

Abstract: A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.

Abstract: An obversely and reversely pluggable connector structure, includes a multi-plate circuit board, first transmission conductor set and second transmission conductor set each, a plurality of first soldering faces and second soldering faces, a plurality of first conduction portions and second conduction portions, a plurality of first through holes and second through hole portions, a first shielding shell and second shielding shell each, first capacitor unit and second capacitor unit each at least, allowing the first transmission conductor set and second transmission conductor set different in length to clamp a connector to the circuit board together through the above components, and components for soldering, conducting, reducing noise are configured correspondingly to each transmission conductor set, thereby achieving the reduction of the volume upon a connector assembly, and having the effect of decreasing EMI (Electromagnetic interference) and RFI (radio frequency interference).

Abstract: An electronic connector includes a transmission conductor group including two rows of spring contacts for insertion into a connector female portion in normal and reverse directions, a transmission conductor pin group, which is formed at a rear side of the transmission conductor group and arranged in a single row, a circuit substrate, which is electrically connected to the transmission conductor pin group, a shielding housing, which receives therein the transmission conductor group, and an inclined cover section, which extends from the shielding housing to shield the transmission conductor pin group. As such, contacts of the transmission conductor group are provided in two rows so that mating between a male portion and a female portion can be made in a directionless manner, allowing for insertion in both normal and reverse directions. The transmission conductor pin group is set in an arrangement of a single row to maintain the convenience of manufacturing.

Abstract: An electronic connector includes a transmission conductor group including two rows of plate-like contacts for insertion of a connector male portion in normal and reverse directions, a transmission conductor pin group, which is formed at a rear side of the transmission conductor group and arranged in a single row, a shielding housing, which receives therein the transmission conductor group, and an inclined cover section, which extends from the shielding housing to shield the transmission conductor pin group. As such, contacts of the transmission conductor group of the connector are provided in an arrangement of two rows so that mating between a male portion and a female portion can be made in a directionless manner, allowing for insertion in both normal and reverse directions. The transmission conductor pin group extending rearward from the transmission conductor group is set in an arrangement of a single row to maintain the convenience of manufacturing.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer.

Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.