Abstract: Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.

Abstract: The present disclosure relates to a CMOS image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A back-side deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a position within the substrate. The BDTI structure comprises a doped layer lining a sidewall surface of a deep trench and a dielectric fill layer filling a remaining space of the deep trench. By forming the disclosed BDTI structure that functions as a doped well and an isolation structure, the implantation processes from a front-side of the substrate is simplified, and thus the exposure resolution, the full well capacity of the photodiode, and the pinned voltage is improved.

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 to 30× that of the amorphous layer. The seed layer stack may be repeated to give a laminate of two amorphous layers and two smoothing layers, and is advantageous for enhancing performance in magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. A template layer such as NiCr may be formed on the uppermost smoothing layer to promote and maintain perpendicular magnetic anisotropy in an overlying magnetic layer during high temperature processing up to 400° C. The amorphous seed layer is SiN, TaN, or CoFeM where M is B or another element with a content that makes CoFeM amorphous as deposited.

Abstract: A head-mounted display (HMD) apparatus includes an HMD device and a liquid crystal (LC) lens device. The HMD device has a light entering surface for entrance of ambient light, and a light exit surface. The HMD device permits passage of the ambient light therethrough to form a real world image for an observer who wears the HMD apparatus, and generates and projects display light toward the light exit surface to form a computer-generated image for the observer. The LC lens device has an adjustable focal length and is disposed to change convergence of the ambient light and the display light from the HMD device, so as to correct vision of the observer.

Abstract: A process flow for shrinking a critical dimension (CD) in photoresist features and reducing CD non-uniformity across a wafer is disclosed. A photoresist pattern is treated with halogen plasma to form a passivation layer with thickness (t1) on feature sidewalls, and thickness (t2) on the photoresist top surface where t2>t1. Thereafter, an etch based on O2, or O2 with a fluorocarbon or halogen removes the passivation layer and shrinks the CD. The passivation layer slows the etch such that photoresist thickness is maintained while CD shrinks to a greater extent for features having a width (d1) than on features having width (d2) where d1>d2. Accordingly, CD non-uniformity is reduced from 2.3% to 1% when d2 is 70 nm and is shrunk to 44 nm after the aforementioned etch. After a second etch through a MTJ stack to form MTJ cells, CD non-uniformity is maintained at 1%.

Abstract: A flexible optical element adopting liquid crystals (LCs) as the materials for realizing electrically tunable optics is foldable. A method for manufacturing the flexible element includes patterned photo-polymerization. The LC optics can include a pair of LC layers with orthogonally aligned LC directors for polarizer-free properties, flexible polymeric alignment layers, flexible substrates, and a module for controlling the electric field. The lens power of the LC optics can be changed by controlling the distribution of electric field across the optical zone.

Abstract: A synthetic antiferromagnetic (SAF) structure for a spintronic device is disclosed and has an FL2/AF coupling/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. In one embodiment, AF coupling is improved by inserting a Co dusting layer on top and bottom surfaces of a Ru AF coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the SAF structure.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: A process flow for forming magnetic tunnel junctions (MTJs) with minimal sidewall residue and reduced low tail population is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask pattern is etch transferred through the underlying MTJ layers including a reference layer/tunnel barrier/free layer stack. The etch transfer may be completed in a single RIE step based on a first flow rate of O2 and a second flow rate of an oxidant such as CH3OH where the CH3OH/O2 ratio is at least 7.5:1. The RIE may also include a flow rate of a noble gas. In other embodiments, a chemical treatment with an oxidant such as CH3OH, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack when the ion beam etch or plasma etch involves noble gas ions.

Abstract: A magnetic tunnel junction (MTJ) that avoids electrical shorts and has improved data retention is disclosed. An uppermost capping layer has a first sidewall that is coplanar with an interface between outer oxidized portions and a center ferromagnetic portion of a free layer (FL) that has a FL width (FLW). A dielectric spacer is formed on the first sidewall and oxidized outer FL portions. The pinned layer (PL) has a width (PLW) substantially greater than FLW, and a second sidewall thereon is formed by a self-aligned etch using the dielectric spacer and capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and dielectric spacer but does not degrade MTJ properties since the sidewall layer does not contact the FL and PL center portions responsible for device performance. PL width>FLW ensures greater capability for data retention especially for FLW<60 nm.

Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.

Abstract: Disclosed is a capacitive touch panel having a circuitous conductor pattern structure. The capacitive touch panel contains a number of first axial conductor assemblies and a number of second axial conductor assemblies, wherein each second axial conductor assembly includes a number of second axial conductor cells which are composed of a number of bar shape figures with accordion shape or wave shape edges. Electrical fields and induced capacitors are generated between adjacent axial conductor assemblies with different directions when giving control signals. Then the touched position is detected. Circuitous conductor pattern increases the region of the first axial conductor assembly and the inducing range of electrical field, thus the amount of the axial conductor assemblies and conduction lines can be reduced.

Abstract: A seed layer stack with a uniform top surface having a peak to peak roughness of 0.5 nm is formed by sputter depositing an amorphous layer on a smoothing layer such as Mg where the latter has a resputtering rate 2 × to 30 × that of the amorphous layer. The uppermost seed (template) layer is NiW, NiMo, or one or more of NiCr, NiFeCr, and Hf while the bottommost seed layer is Ta or TaN, for example. Accordingly, perpendicular magnetic anisotropy in an overlying magnetic layer is maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded memory devices, or read head sensors. The amorphous seed layer is SiN, TaN, or CoFeM where M may be B.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.

Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and damage is disclosed wherein a pattern is first formed in a hard mask or uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers with a RIE process comprising main etch and over etch portions, and a cleaning step. The RIE process features noble gas and an oxidant that is one or more of CH3OH, C2H5OH, NH3, N2O, H2O2, H2O, O2, and CO. Noble gas/oxidant flow rate ratio during over etch may be greater than during main etch to avoid chemical damage to MTJ sidewalls. The cleaning step may comprise plasma or ion beam etch with the noble gas and oxidant mixture. Highest values for magnetoresistive ratio and coercivity (Hc) are observed for noble gas/oxidant ratios from 75:25 to 90:10, especially for MTJ nanopillar sizes ?100 nm.

Abstract: A process flow for forming and encapsulating magnetic tunnel junction (MTJ) nanopillars is disclosed wherein MTJ layers including a reference layer (RL), free layer (FL), and tunnel barrier layer (TB) are first patterned by reactive ion etching or ion beam etching to form MTJ sidewalls. A plurality of MTJs on a substrate is heated (annealed) at a station in a process chamber to substantially crystallize the RL, FL, and TB to a body centered cubic (bcc) structure without recrystallization from the edge of the device before an encapsulation layer is deposited thereby ensuring lattice matching between the RL and TB, and between the FL and TB. The encapsulation layer is deposited at the same station as the anneal step without breaking vacuum, and preferably using a physical vapor deposition to prevent reactive species from attacking MTJ sidewalls. Magnetoresistive ratio is improved especially for MTJs with critical dimensions below 70 nm.

Abstract: The present disclosure, in some embodiments, relates to a CMOS image sensor. The CMOS image sensor has an image sensing element disposed within a substrate. A plurality of isolation structures are arranged along a back-side of the substrate and are separated from opposing sides of the image sensing element by non-zero distances. A doped region is laterally arranged between the plurality of isolation structures. The doped region is also vertically arranged between the image sensing element and the back-side of the substrate. The doped region physically contacts the image sensing element.

Abstract: Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler grid portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler grid portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a well region on the semiconductor substrate, a radio frequency circuit, a first guard ring adjacent to the RF circuit, and a first isolation region directly disposed between the RF circuit and the first guard ring. The well region has a first conductive type. The RF circuit includes a FIN field-effect transistor having a plurality of first fins and a plurality of first polys on the well region, wherein the first polys are perpendicular to the first fins. The first guard ring includes a plurality of second fins and a pair of second polys on the well region, wherein the second polys are perpendicular to the second fins. The first fins are arranged parallel to the second fins, and the first fins are separated from the second fins by the first isolation region.

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.