Abstract: A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method further includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and forming a conductive structure over and electrically connected to the thermal control mechanism. The method further includes forming a second dielectric layer over the first dielectric layer and surrounding the conductive structure.

Abstract: A voltage-controlled oscillator device includes first and second voltage-controlled oscillators, a first switch group including two first switches, and a second switch group including two second switches. The first voltage-controlled oscillator includes a first inductor group, a first negative resistance circuit and a first voltage output terminal group. The second voltage-controlled oscillator includes a second inductor group, a second negative resistance circuit and a second voltage output terminal group. For the first switch group, first control terminals are electrically connected to the first voltage output terminal group, first input terminals are electrically connected to the second voltage output terminal group, first output terminals are electrically connected.

Abstract: A communications system includes at least one receiver having receiving elements and a transmitter having transmitting elements to transmit signals to the receiving elements via wireless propagation channels. The transmitter includes a beam-forming network and a channel measurement unit. The beam-forming network receives input signal streams at its input ports and outputs one or more signals as shaped beams based on a set of composited transfer functions. The channel measurement unit performs measurements of components of channel status information to generate a set of point-to-point transfer functions and generates the composited transfer functions by computing linear combinations of the point-to-point transfer functions. Each of the point-to-point transfer functions characterizes propagation paths from one of the transmitting elements to one of the receiving elements.

Abstract: A nanonetwork with controlled chirality prepared via self-assembly of triblock terpolymers, wherein each of the triblock terpolymers includes a first block, a second block and a third block. The first block is connected to the second block, and the third block is connected to the second block. The first block, the second block and the third block are incompatible. The third block has a homochiral characteristic, and a chirality of the nanonetwork with controlled chirality is determined by the homochiral characteristic.

Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.

Abstract: A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A touch control method is provided. The method includes: providing a touch device with multiple touch electrodes; determining whether an object is located in a sensing distance; detecting a sensing group sensing the object if the determination is yes; determining whether an electrode amount in the electrode group is between a first value and a second value; determining whether a sensing time of a predetermined proportion of the touch electrodes in the sensing group is equal to or greater than a predetermined time; executing a fingerprint recognition mode if the electrode amount is between the first value and the second value, and the sensing time is equal to or greater than the predetermined time; executing a touch operation mode if the electrode amount is less than the first value or greater than the second value, or the sensing time is less than the predetermined time.

Abstract: The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.

Abstract: The present invention relates to a method for treating a side effect caused by bacillus Calmette-Guérin (BCG) perfusion therapy for bladder cancer. The method includes: administering a Chinese medicine composition to a subject in need thereof; wherein the Chinese medicine composition is an extract of a first mixture comprising Gentiana scabra, Scutellariae Radix, Gardeniae Fructus, Angelicae Sinensis Radix, Rehmanniae radix, Akebiae Caulis, Bupleurum chinense, Plantaginis Semen, Atractylodes lancea, Rhizoma alismatis, and Glycyrrhiza uralensis.

Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: A card device and a manufacturing method thereof are disclosed. The card device includes a first substrate, a circuit board, a sensing module and a second substrate. The circuit board is disposed on the first substrate, and the circuit board includes an accommodating recess. The sensing module is disposed in the accommodating recess. The sensing module includes a sensing unit and a protective layer formed on the sensing unit, and the sensing unit is electrically connected to the circuit board. The second substrate is disposed on the circuit board. The second substrate includes an opening, and the opening exposes the protective layer.

Abstract: A heat dissipation device is provided, including a main body, a plurality of fins, a plurality of flat tubes, a pump head, and a fan. The pump head and the fan are disposed on opposite sides of the main body. The main body has three tanks arranged along the long axis of the main body. The flat tubes communicate with the tanks. The fins are disposed on the flat tubes.

Abstract: An electronic panel includes a first substrate; a conductive line disposed on the first substrate and extending along a first direction; a conductive element extending along a second direction perpendicular to the first direction; and an active layer disposed between the conductive element and the first substrate. In a top view, the active layer includes a first overlapping region overlapping a portion of the conductive line; a first contact region electrically connected to a connecting portion of the conductive element through a first via hole; and a turning region between the first overlapping region and the first contact region. The turning region doesn't extend along the first direction and the second direction.

Abstract: In one implementation, a method of including a person in a CGR experience or excluding the person from the CGR experience is performed by a device including one or more processors, non-transitory memory, and a scene camera. The method includes, while presenting a CGR experience, capturing an image of scene; detecting, in the image of the scene, a person; and determining an identity of the person. The method includes determining, based on the identity of the person, whether to include the person in the CGR experience or exclude the person from the CGR experience. The method includes presenting the CGR experience based on the determination.

Abstract: An apparatus includes N audio receivers positioned in a pre-defined geometry with respect to P audio sources to receive P audio signals from the P audio sources; N data sets coupled to the N audio receivers to sample the received P audio signals into N data streams; a plurality of storage devices coupled to the N data sets to store the N data streams; and a post processor coupled to the plurality of storage devices to generate output signals corresponding to reconstituted P audio signals using a wavefront demultiplexing transformation, wherein N and P are positive integers and N?P. The post processor has inputs receiving data retrieved from the plurality of storage devices and outputs providing the output signals.

Abstract: The present disclosure provides a sensing device including a substrate and a sensing pixel. The sensing pixel is disposed on the substrate and includes an electrode and a thermistor. The thermistor is electrically connected to the electrode and is separated from the substrate by an air gap. When the sensing pixel is operated in a period, the electrode receives a voltage, and a part of the thermistor moves toward the substrate, such that the thermistor is in thermal conduction with the substrate.

Abstract: Systems and methods for estimating a layout of a room are disclosed. The room layout can comprise the location of a floor, one or more walls, and a ceiling. In one aspect, a neural network can analyze an image of a portion of a room to determine the room layout. The neural network can comprise a convolutional neural network having an encoder sub-network, a decoder sub-network, and a side sub-network. The neural network can determine a three-dimensional room layout using two-dimensional ordered keypoints associated with a room type. The room layout can be used in applications such as augmented or mixed reality, robotics, autonomous indoor navigation, etc.

Abstract: A sensing device, including a plurality of sensing pixels arranged in Y rows and M columns, a plurality of readout lines coupled to the sensing pixels, and a plurality of control lines each coupled to a sensing pixel subset, is provided. The Y times N sensing pixels within the sensing pixel subset are arranged in adjacent N columns, where Y, M and N are integers and N is smaller than M. Each of the control lines is configured to control one row of the sensing pixel subset to output signals through corresponding readout lines.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.