Abstract: A metal plate to be used in the manufacture of a deposition mask comprises: a base metal plate; and a surface layer disposed on the base metal plate, wherein the surface layer includes elements different from those of the base metal plate, or has a composition ratio different from that of the base metal plate, and an etching rate of the base metal plate is greater than the etching rate of the surface layer. An embodiment includes a manufacturing method for a deposition mask having an etching factor greater than or equal to 2.5. The deposition mask of the embodiment includes a deposition pattern region and a non-deposition region, the deposition pattern region includes a plurality of through-holes, the deposition pattern region is divided into an effective region, a peripheral region, and a non-effective region, and through-holes can be formed in the effective region and the peripheral region.

Abstract: In an embodiment, a method includes: spinning a wafer around an axis of rotation at a center of the wafer; applying a first stream of liquid along a line starting from an initial point on the wafer adjacent to the center of the wafer, through the center of the wafer, and ending at an edge of the wafer; applying a second stream of liquid to an inner third of the line starting at the initial point and ending at a boundary point; applying a third stream of liquid to a middle third of the line starting at the boundary point; applying a fourth stream of liquid to an outer third of the line ending at the edge of the wafer; applying a fifth stream of liquid along the line starting from the initial point and ending at the edge of the wafer; and applying a stream of gas along the line starting from the initial point and ending at the edge of the wafer.

Abstract: A plug connector includes an insulating body, an elastic latch, and a blocking bar. The blocking bar is connected to the insulating body and spans a pushing portion of the elastic latch. The pushing portion has at least one hook and a pushing end hung in the air. The blocking bar is located between the hook and the pushing end for protecting the pushing end.

Abstract: A display panel includes a first substrate; a scan line and a data line disposed on the first substrate and extending in a first direction and a second direction, respectively, wherein the data line intersects the scan line; a polysilicon layer disposed on the first substrate. In a top view, the polysilicon layer includes: a first channel region overlapping a portion of the scan line; a second channel region overlapping another portion of the scan line; a non-channel region not overlapping the scan line and connected between the first channel region and the second channel region; a long region extended in the second direction; wherein a portion of the non-channel region extends in the first direction, the portion has a first width in the second direction, the long region has a second width in the first direction, and the first width is greater than the second width.

Abstract: An electronic device includes a first transistor, a second transistor, and a sensing circuit coupled to at least one of the first transistor and the second transistor. The sensing circuit includes a diode, a third transistor, and a fourth transistor. The diode has a first terminal. The third transistor has a first terminal and a second terminal. The first terminal of the third transistor is coupled to the first terminal of the diode. The fourth transistor has a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a data driver.

Abstract: An optical sensing module and an electronic device are provided. The optical sensing module includes a substrate, a plurality of optical sensing elements, and a light-blocking element. The substrate has a sensing region and a non-sensing region around the sensing region. The plurality of optical sensing elements is disposed on the sensing region. The light-blocking element is disposed on the non-sensing region and a portion of the sensing region. The light-blocking element overlaps a portion of the plurality of optical sensing elements in a normal direction of the substrate.

Abstract: An electronic device is provided. The electronic device includes a substrate, an optical sensing element, a light-shielding structure, and a microlens. The substrate has a normal direction. The optical sensing element is disposed on the substrate. The light-shielding structure is disposed on the optical sensing element and includes a plurality of light-shielding layers. Each light-shielding layer includes an opening, and centers of the openings are arranged along a first direction and separated from each other. The microlens is disposed on the light-shielding layers and overlaps the opening of the uppermost light-shielding layer. The microlens guides light into an optical channel formed by the openings, so that the optical sensing element has a maximum response value for light with an incident angle that is greater than or equal to 10 degrees and less than or equal to 30 degrees relative to the normal direction.

Abstract: Various implementations disclosed herein include devices, systems, and methods that enable faster and more efficient real-time physical object recognition, information retrieval, and updating of a CGR environment. In some implementations, the CGR environment is provided at a first device based on a classification of the physical object, image or video data including the physical object is transmitted by the first device to a second device, and the CGR environment is updated by the first device based on a response associated with the physical object received from the second device.

Abstract: An input switching circuit dynamically connects, based on an input mapping table, input streams to inputs of a wavefront pre-transform circuit. An output switching circuit dynamically connects, based on an output mapping table, output data at outputs of the wavefront pre-transform circuit to transport streams. A controller controls, based on a wiping command, at least one of the input and output switching circuits to alter at least one of the input and output mapping tables such that the at least one of the input and output switching circuits is disabled for connection. A first subset of the transport streams operates in a foreground mode available to a user and is transported for storage in remote storage sites at a network and a second subset of the transport streams operates in a background mode available to an administrator and is not transported for storage in the remote storage sites.

Abstract: An optical circuit includes one or more input waveguides, a plurality of output waveguides, and a reflector structure. At least a portion of the reflector structure forms an interface with the one or more input waveguides. The portion of the reflector structure has a smaller refractive index than the one or more input waveguides. An electrical circuit is electrically coupled to the optical circuit. The electrical circuit generates and sends different electrical signals to the reflector structure. In response to the reflector structure receiving the different electrical signals, a carrier concentration level at or near the interface or a temperature at or near the interface changes, such that incident radiation received from the one or more input waveguides is tunably reflected by the reflector structure into a targeted output waveguide of the plurality of output waveguides.

Abstract: A photonic heater is provided. The photonic heater includes a current source and a transfer circuit. The transfer circuit connected to the current source. The photonic heater further includes a heating element. The heating element is connected to the transfer circuit. The transfer circuit is operable to regulate an amount of current being transferred from the current court to the heating element.

Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

Abstract: A three-dimensional AND flash memory device includes a gate stack structure and a silt. The silt extends along a first direction and divides the gate stack structure into a plurality of sub-blocks. Each sub-block includes a plurality of rows, and each row includes a plurality of channel pillars, a plurality of charge storage structures, and a plurality of pairs of conductive pillars. The plurality of pairs of conductive pillars are arranged in the plurality of channel pillars and penetrate the gate stack structure, and are respectively connected to the plurality of channel pillars. Each pair of conductive pillars includes a first conductive pillar and a second conductive pillar separated from each other along a second direction. There is an acute angle between the second direction and the first direction.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.

Abstract: The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.

Abstract: An electronic device including a substrate, a thin film transistor, a micro pump, and a micro fluid platform is provided. The thin film transistor is disposed on the substrate. The micro pump is disposed on the substrate and electrically connected to the thin film transistor. The micro fluid platform is disposed on the substrate and coupled to the micro pump. The micro pump is configured to travel a to-be-test sample to the micro fluid platform.

Abstract: A detection circuit is provided herein, which includes a first transistor, a second transistor, a third transistor, a light sensor, a capacitor, and a fourth transistor. The first transistor has a control terminal, a first terminal, and a second terminal. The second transistor is coupled to the control terminal. The third transistor is coupled to the control terminal and the second terminal. The light sensor is coupled to the control terminal. The capacitor is coupled to the control terminal. The fourth transistor is coupled to the second terminal.

Abstract: A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

Abstract: The display device includes a first substrate; an active layer disposed on the first substrate; a first insulation layer disposed on the active layer; a first electrode layer disposed on the first insulation layer including a gate electrode line extending along a first direction and a protruding portion extending along a second direction; a second insulation layer disposed on the first electrode layer; and a second electrode layer disposed on the second insulation layer. The second electrode layer includes a date line extending along the second direction and a conductive layer. The conductive layer includes a first conductive portion and a second conductive portion, wherein the first conductive portion has a first maximum width A along the first direction, and the second conductive portion has a second maximum width B along the first direction. The first maximum width A is less than the second maximum width B.