Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.

Abstract: Disclosed are a display device and a backlight control method for the display device. The display device includes a display panel, a backlight source, a first computing unit, and a second computing unit. The display panel includes a first display region and a second display region. The first light-emitting region corresponds to the first display region. The second light-emitting region corresponds to the second display region. The first computing unit calculates a first brightness distribution within a first range. The second computing unit calculates a second brightness distribution within a second range. The first light-emitting region emits light according to the first brightness distribution. The second light-emitting region emits light according to the second brightness distribution.

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.

Abstract: An in-mold electronic (IME) device includes a curved substrate, a first conductive layer, a dielectric layer, a gap compensation layer, and a second conductive layer. The curved substrate has a first surface. The first conductive layer is disposed on the first surface. The dielectric layer is disposed on the first conductive layer and has a first thickness. The gap compensation layer is disposed on the first surface and connected to the dielectric layer. The gap compensation layer has a second thickness. The second conductive layer is disposed on the gap compensation layer and electrically connected to the gap compensation layer. A curvature radius of the curved substrate is c, a ratio of the second thickness to the first thickness is r, and c and r satisfy a relationship: r=1.5?0.02c±15%.

Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.

Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.

Abstract: A light-emitting diode and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, an LED wafer is provided. The LED wafer includes a substrate and a light-emitting semiconductor stacking structure positioned on the surface of the substrate. The light-emitting semiconductor stacking structure includes a first type semiconductor layer, an active layer, and a second type semiconductor layer from a side of the substrate. Second, dicing lanes are defined on the upper surface of the LED wafer. Third, dicing is performed along the dicing lanes of the substrate using a laser. The laser is focused on the lower surface of the substrate to form a surface hole and focused inside the substrate to form an internal hole. The diameter of the surface hole is greater than the diameter of the internal hole. Fourth, the LED wafer is separated into LED chips along the dicing lanes.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: An organic optoelectronic device comprises a first electrode, an active layer and a second electrode. Active layer materials of the active layer comprise a block conjugated polymer materials which includes a structure of formula I: The polymer 1 is a p-type polymer with high energy gap, and the polymer 1 comprises a first electron donor and a first electron acceptor arranged alternately. The polymer 2 is a p-type polymer with low energy gap, and the polymer 2 comprises a second electron donor and a second electron acceptor arranged alternately. Wherein, o and p>0. The organic optoelectronic device of the present invention transfers carriers through the polymer 2 with low energy gap, and suppresses the recombination probability of carriers through the polymer 1 with high energy gap, thereby reducing the leakage current of the organic optoelectronic device.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A device model parameter generation system, comprises a user module, for obtaining parameter set configurations and measurement data of devices; a parameter extraction module, for performing parameter extractions on the parameter set configurations and the measurement data, to generate a parameter set; a simulation module, for performing simulations according to the parameter set configurations and the measurement data, to generate a simulation results; an analysis module, for determining whether the devices conform to a trend according to the parameter set, to generate a first determination result, and for determining whether the devices conform to a smoothness according to the first determination result and the parameter set, to generate a second determination result; and a device model parameter generation module, for generating a device model parameters according to the second determination result and the parameter set.

Abstract: A wearable stimulation device includes a wearable member, a stimulation unit, and a driver. The stimulation unit is secured to the wearable member. The stimulation unit includes an immovable end, a stimulation end, and a power element. The power element is connected between the immovable end and the stimulation end for driving the stimulation end to reciprocate relative to the immovable end. The driver is in signal connection with the power element. The driver is configured to output a vibration signal to the power element for the stimulation end to have a stroke of between 8.8 mm and 10.8 mm, a thrust of between 5.6 N and 7.6 N and a reciprocating frequency of between 180 Hz and 220 Hz, thereby stimulating the deep muscles of the abdomen or waist of a human body without affecting the superficial muscles.

Abstract: A solid modeling and non-fungible virtual and anti-counterfeiting integration system mainly comprises a 3D modeling device, an elliptic curve cryptographic module, and a non-fungible transaction platform. The 3D modeling device mainly obtains a 3D image file with a characteristic value from a physical object, the elliptic curve cryptographic module generates a sub-public key and a sub-private key, and the non-fungible transaction platform comprises a master private key and a master public key. The sub-public key is capable of encrypting the characteristic value, the sub-private key decrypts the sub-public key to restore the characteristic value and display the 3D image file, the master private key signs the sub-public key and the sub-private key, the master public key verifies the signature, by obtaining the sub-public key and the sub-private key, the sub-private key is capable of decrypting the sub-public key to restore the characteristic value and display the 3D image file.