Abstract: A power converting module includes a generator-side converting circuit, a grid-side converting circuit, and a controlling and driving circuit. The generator-side converting circuit is configured to receive an input voltage and output a first current according to the input voltage. The grid-side converting circuit is electrically coupled to the generator-side converting circuit at a node, and configured to receive the first current and supply power to a grid according to the first current. The controlling and driving circuit is configured to output a driving signal to the grid-side converting circuit to control a voltage level at the node through the grid-side converting circuit, in which a voltage at the node is within a medium voltage (MV) level.

Abstract: A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type memory; allocating a page from the first type memory according to a system request, and inserting the page into the inactive list accordingly; moving the page from the inactive list to the write active list or the read active list in response to two or more successive access operations on the page; and referring the page to a physical address on the second type memory when the page is in the write active list.

Abstract: An operating method of a memory controller, for a memory device including a plurality of cells, includes steps of: checking states of the cells; marking at least one specific bit-channel according to the states of the cells; and performing an uneven wear leveling scheme on at least one target cell storing messages from the at least one specific bit-channel, such that the wear level of the at least one target cell is different from other cells.

Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

Abstract: A DC conversion device including a first DC converter and a second DC converter connected in series, a voltage difference adjusting unit, and a first and a second control unit is provided. The first and the second DC converter respectively receive a first and a second input current to generate a first output current and a first output voltage, a second output current and a second output voltage at a first and a second output end connected to a first and a second energy-storing element, respectively. The voltage difference adjusting unit generates a voltage difference adjusting signal. The first control unit generates a first control signal to control the first converter. The second control unit generates a second control signal according to the voltage difference adjusting signal to control the second converter to balance the first and the second input and output voltages.

Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.

Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

Abstract: A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.

Abstract: A smart pet interactive device includes a cloud server, a smart communication device and a wireless pet interactive device. The smart communication device wireless is connected to the cloud server and equipped with an interactive module corresponding to the cloud server. The wireless pet interactive device wireless is connected to the cloud server and placed in a living space where at least one pet lives. The smart communication device is connected to the cloud server through the interactive module to control the wireless pet interactive device to provide food to the at least one pet, capture a first image of the living space, send the first image to the smart communication device through the cloud server, and control the interactive module to display the first image, thereby effectuating interaction between a pet and its owner.

Abstract: A smart cloud-based interactive aquarial device, mounted on an aquarium and connected to at least one cloud server to communicate with an electronic device through the cloud server, including an image capturing device for capturing images in the aquarium; at least one peripheral control device including a feeding member for feeding fish foods into the aquarium automatically or according to a feeding instruction of the electronic device; a processing module connected to the image capturing device and the peripheral control device to control operation thereof; and a wireless communication module for enabling the smart cloud-based interactive aquarial device to communicate with the cloud server or the electronic device, sending images captured by the image capturing device to the cloud server for storage and sending at least one instruction to the processing module through the cloud server.

Abstract: A power supply includes power modules. Each of the power modules includes an input stage and an output stage. The input stage generates an intermediate voltage, and the output stage outputs a DC supply voltage according to the intermediate voltage. The input stages are controlled with at least one first common control signal having a common duty cycle, and the output stages are controlled with at least one second common control signal having a common duty cycle.

Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract: A DC conversion device including a first DC converter and a second DC converter connected in series, a voltage difference adjusting unit, and a first and a second control unit is provided. The first and the second DC converter respectively receive a first and a second input current to generate a first output current and a first output voltage, a second output current and a second output voltage at a first and a second output end connected to a first and a second energy-storing element, respectively. The voltage difference adjusting unit generates a voltage difference adjusting signal. The first control unit generates a first control signal to control the first converter. The second control unit generates a second control signal according to the voltage difference adjusting signal to control the second converter to balance the first and the second input and output voltages.