Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. The gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. The source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. The first doped region is disposed in the substrate and adjacent to the source region. The second doped region is disposed in the substrate and located under the first doped region. The conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.

Abstract: A laser welding method for steel plates and a profile steel welded by laser welding are disclosed. The laser welding method comprises the following steps of connecting a first steel plate and a second steel plate to form a joint; and using a laser to weld the joint to form a profile steel. The laser has a laser power between 10,000 and 25,000 watts. A weld bead is formed at the joint. The weld bead has a weld depth and a weld width. The ratio of the weld depth to the weld width is between 1 and 5. Thus, the process can be simplified effectively, the welding time can be shortened, and the processing area can be reduced.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

Abstract: An interactive system combines an automated voice mechanism with a visual feedback mechanism. A first terminal device and a telecommunications server mutually transmit messages through a public switched telephone network. The first terminal device can send an input message to the telecommunications server and receive a voice feedback message from the telecommunications server. The telecommunications server can generate a processing message based on the input message and transmit the processing message to an information management server which based on the processing message's content, through an internet sends a forward message to an information distribution server which based on the forward message's content, sends a control message to a second terminal device. The second terminal device transmits a request message to a picture content management server according to the forward message to obtain a picture feedback message returned by the picture content management server.

Abstract: A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.

Abstract: This document describes techniques and systems related to tracking different sections of articulated vehicles. A vehicle uses a radar system that can discern between unarticulated vehicles and articulated vehicles, which by definition have multiple sections that can pivot in different directions for turning or closely following a curve. The radar system obtains detections indicative of another vehicle traveling nearby. When the detections indicate the other vehicle is articulated, the radar system tracks each identifiable section, rather than tracking all the sections together. A bounding box is generated for each identifiable section; the radar system separately and concurrently monitors a velocity of each bounding box. The multiple bounding boxes that are drawn enable the radar system to accurately track each connected section of the articulated vehicle, including to detect whether any movement occurs between two connected sections, for accurately localizing the vehicle when driving.

Abstract: A moisture-permeable composite membrane is manufactured by the step of subjecting a mixture to a crosslinking treatment. The mixture contains a polyisoprene, a polyurethane with a polar functional group, a crosslinking agent, and a vulcanizing agent. In the mixture, a weight ratio of the polyurethane with the polar functional group to the polyisoprene ranges from 1:0.55 to 1:6.60. A method for manufacturing the moisture-permeable composite membrane is also provided.

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.