Abstract: A method for fabricating a semiconductor device includes the steps of defining a scribe line on a front side of a wafer, forming an inter-metal dielectric (IMD) layer on the wafer, forming an alternating stack on the IMD layer, removing the alternating stack to form a trench, forming a passivation layer extending from the alternating stack to the trench, and then performing a dicing process along the scribe line to dice the passivation layer and the wafer.

Abstract: A method of manufacturing a magnetoresistive random access memory, including forming a conductive plug in a substrate, forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode material layer on the substrate and the conductive plug, and performing an anisotropic etch process to pattern the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode material layer, thereby forming a magnetic memory cell on the conductive plug, wherein the anisotropic etch process overetches the conductive plug and the substrate so that a notched portion is formed on one side of an upper edge of the conductive plug, and depressed regions are formed on the substrate at two sides of the magnetic memory cell.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.

Abstract: A method for preparing a recycled plastic includes the steps of: (a) mixing a waste plastic with a depolymerizing agent, followed by subjecting the waste plastic to a depolymerization reaction, so as to obtain a depolymerized product; (b) mixing the depolymerized product with a first polyether polyol to obtain a first mixture, followed by subjecting the first mixture to a polymerization reaction, so as to obtain a polymeric diol mixture; and (c) mixing the polymeric diol mixture with a second polyether polyol, a multi-functional isocyanate, and a solvent to obtain a second mixture, followed by subjecting the second mixture to a reaction, thereby obtaining the recycled plastic having a carbamate group. A recycled plastic prepared by the aforesaid method, a non-porous film or a microporous film obtained from the recycled plastic, and a composite fabric including the non-porous film or the microporous film are also provided.

Abstract: A semiconductor structure includes a substrate having a memory device region covered by a first dielectric layer, a memory stack structure on the first dielectric layer, an insulating layer conformally covering the memory stack structure and the first dielectric layer, a second dielectric layer on the insulating layer, an etching stop layer on the second dielectric layer, a third dielectric layer on the etching stop layer, and a second interconnecting structure through the third dielectric layer, the etching stop layer and the insulating layer to contact a top surface of the memory stack structure. The insulating layer directly contacts a bottom surface of the etching stop layer and partially covers a bottom surface and a lower sidewall of the second interconnecting structures.

Abstract: A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate, a stress tuning structure and a first bonding structure. The stress tuning structure is disposed on the first substrate. The stress tuning structure includes a first oxide layer and a second oxide layer sequentially disposed on the first substrate, and a first refractive index of the first oxide layer is different from a second refractive index of the second oxide layer. The first bonding structure is disposed on the stress tuning structure. The second wafer includes a second substrate and a second bonding structure. The second bonding structure is disposed on the second substrate. The second bonding structure is bonded with the first bonding structure.

Abstract: Disclosed herein is a recombinant antibody or a fragment thereof exhibiting binding affinity and specificity toward B7-H3. According to some embodiments of the present disclosure, the recombinant antibody or its fragment comprises a heavy chain variable (VH) domain and a light chain variable (VL) domain respectively having the amino acid sequences of SEQ ID NOs: 7 and 8. Also disclosed herein are an immunoconjugate comprising the recombinant antibody or its fragment, and a method of treating cancers by use of the present immunoconjugate.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A wireless USB interface extender connected wirelessly during use in a wireless projection system is provided. When operating in a station mode, the wireless USB interface extender communicates with a conversion device by using a first wireless transmission unit. The conversion device is coupled to a display device. When operating in an access point mode, the wireless USB interface extender communicates with at least one other wireless USB interface extender, each being coupled to at least one USB device, by using a second wireless transmission unit. When the wireless USB interface extender operates in the station mode and the access point mode at the same time, the control unit processes a to-be-displayed picture and a signal corresponding to at least one of the at least one USB device to generate an integrated signal, transmitted to the display device through the conversion device for displaying on the display device.

Abstract: A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

Abstract: The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.

Abstract: A capacitor includes cup-shaped lower electrodes disposed on a substrate, a capacitor dielectric layer conformally covering inner surfaces and outer surfaces of the cup-shaped lower electrodes, and a support layer disposed between outer surfaces of the cup-shaped lower electrodes to connect the cup-shaped lower electrodes. The capacitor further includes an annealed oxide layer, which is interposed between the inner surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer, and is also interposed between a portion of the outer surfaces of the cup-shaped lower electrodes and the capacitor dielectric layer. A method for forming the capacitor is also provided.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. The gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. The source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. The first doped region is disposed in the substrate and adjacent to the source region. The second doped region is disposed in the substrate and located under the first doped region. The conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.

Abstract: A laser welding method for steel plates and a profile steel welded by laser welding are disclosed. The laser welding method comprises the following steps of connecting a first steel plate and a second steel plate to form a joint; and using a laser to weld the joint to form a profile steel. The laser has a laser power between 10,000 and 25,000 watts. A weld bead is formed at the joint. The weld bead has a weld depth and a weld width. The ratio of the weld depth to the weld width is between 1 and 5. Thus, the process can be simplified effectively, the welding time can be shortened, and the processing area can be reduced.