Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

Abstract: The present disclosure provides an apparatus and a method for polishing a semiconductor substrate in semiconductor device manufacturing. The apparatus can include: a carrier configured to hold the substrate; a polishing pad configured to polish a first surface of the substrate; a chemical mechanical polishing (CMP) slurry delivery arm configured to dispense a CMP slurry onto the first surface of the substrate; and a pad conditioner configured to condition the polishing pad. In some embodiments, the pad conditioner can include: a conditioning disk configured to scratch the polishing pad; a conditioning arm configured to rotate the conditioning disk; a plurality of magnetic screws configured to secure the conditioning disk onto the conditioning arm and including a respective plurality of screw heads; and a plurality of blocking devices respectively positioned beneath the plurality of screw heads and configured to block debris particles from entering a respective plurality of screw holes.

Abstract: This document describes radar tracking with model estimates augmented by radar detections. An example tracker analyzes information derived using radar detections to enhance radar tracks having object measurements estimated from directly analyzing data cubes with a model (e.g., a machine-learning model). High-quality tracks with measurements to objects of importance can be quickly produced with the model. However, the model only estimates measurements for classes of objects its training or programming can recognize. To improve estimated measurements from the model, or even in some cases, to convey additional classes of objects, the tracker separately analyzes detections. Detections that consistently align to objects recognized by the model can update model-derived measurements conveyed initially in the tracks. Consistently observed detections that do not align to existing tracks may be used to establish new tracks for conveying more classes of objects than the model can recognize.

Abstract: A video and audio streaming transmission system is provided. The video and audio streaming transmission system includes a receiving end module, a first transmitting end module and a second transmitting end module. The first transmitting end module obtains a first audio signal, and sends the first audio signal to the receiving end module. The second transmitting end module obtains a second audio signal, and sends the second audio signal to the receiving end module. The receiving end module returns a processed audio signal to the first computer device according to the first audio signal and the second audio signal, so that the first computer device provides the processed audio signal to a conference module.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: An automated plate shaping and verification system allows for the accurate and efficient transformation of a metal plate from a starting shape to a target shape. Using a method for path planning, the system can select heating patterns based on modeling the expected deformation of a particular material type and thickness and identifying candidate heating paths that will sufficiently cause the plate to transform towards the target shape.

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.

Abstract: A wireless briefing device includes a first antenna, a second antenna, and a ground plane. Each of the first antenna and the second antenna couples out a frequency band. A distance between the first antenna and the ground plane is between 0.2 and 0.3 times of a wavelength of the frequency band, and a distance between the second antenna and the ground plane is between 0.2 and 0.3 times of the wavelength of the frequency band.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a second SOT layer on the first SOT layer, a hard mask between the first SOT layer and the second SOT layer, and a spacer adjacent to the MTJ, the first SOT layer, and the hard mask.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a spacer adjacent to the MTJ and the first SOT layer, and a second SOT layer on the first SOT layer. Preferably, the first SOT layer and the second SOT layer are made of same material.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

Abstract: The present disclosure provides an apparatus and a method for polishing a semiconductor substrate in semiconductor device manufacturing. The apparatus can include: a carrier configured to hold the substrate; a polishing pad configured to polish a first surface of the substrate; a chemical mechanical polishing (CMP) slurry delivery arm configured to dispense a CMP slurry onto the first surface of the substrate; and a pad conditioner configured to condition the polishing pad. In some embodiments, the pad conditioner can include: a conditioning disk configured to scratch the polishing pad; a conditioning arm configured to rotate the conditioning disk; a plurality of magnetic screws configured to secure the conditioning disk onto the conditioning arm and including a respective plurality of screw heads; and a plurality of blocking devices respectively positioned beneath the plurality of screw heads and configured to block debris particles from entering exiting a respective plurality of screw holes.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer, and patterning the second SOT layer and the passivation layer.

Abstract: A method of manufacturing a magnetoresistive random access memory, including forming a conductive plug in a substrate, forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode material layer on the substrate and the conductive plug, and performing an anisotropic etch process to pattern the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode material layer, thereby forming a magnetic memory cell on the conductive plug, wherein the anisotropic etch process overetches the conductive plug and the substrate so that a notched portion is formed on one side of an upper edge of the conductive plug, and depressed regions are formed on the substrate at two sides of the magnetic memory cell.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.