Abstract: A floating image generation device is disclosed, which includes a light source, an image generation module, and a floating image generation unit. The image generation module is disposed above the light source and includes a shading unit and an image generation unit. The shading unit is capable of changing light transmissivity state. The image generation unit is disposed above the shading unit. The floating image generation unit is disposed above the image generation unit. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a first floating image when the shading unit is in a first light transmissivity state. The light source emits a light passing through the shading unit, the image generation unit, and the floating image generation unit to generate a second floating image when the shading unit is in a second light transmissivity state.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A test device includes a power compensation module and a test module. The power compensation module receives AC power generated by a device under test to generate DC power to the device under test. The test module provides a plurality of test signals and a test mode to the device under test for testing the device under test.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: The present invention discloses a battery module and a power arrangement method. The battery module includes a battery unit, an energy storage element, a switch, a functional circuit and a control unit. The energy storage element is coupled to the battery unit. The switch is coupled to the energy storage element. The functional circuit is respectively coupled to the battery unit and the energy storage element. The control unit is respectively coupled to the functional circuit and the switch, configured to control the functional circuit to cause the energy storage element to be coupled to the battery unit so that the battery unit charges the energy storage unit, or configured to control the functional circuit to cause the energy storage element to be decoupled with the battery unit so that a discharge path is formed.

Abstract: An optical device is provided. The optical device has a central region and a first-type region surrounding the central region. The first-type region includes a first sub-region and a second sub-region between the central region and the first sub-region. The optical device includes a substrate. The optical device also includes a meta-structure disposed on the substrate. The meta-structure includes first pillars in the first sub-region and second pillars in the second sub-region. In the cross-sectional view of the optical device along the radial direction of the optical device, two adjacent first pillars have a first pitch, two adjacent second pillars have a second pitch, and the second pitch is greater than the first pitch.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: A method includes depositing a first dielectric layer on a first substrate of a first device die, etching the first dielectric layer to form a trench, depositing a metallic material in the trench and on a top surface of the first dielectric layer, and performing a chemical mechanical polish (CMP) process to remove a portion of the metallic material from the top surface of the first dielectric layer to form a first metal pad. After the performing of the CMP process, the method selectively etches the first metal pad to form recesses at an edge portion of the first metal pad, deposits a second dielectric layer on a second substrate of a second device die, forms a second metal pad in the second dielectric layer, and bonds the second device die to the first device die.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

Abstract: The invention discloses a movable locking ear and an electrical device. The electrical device comprises a frame and a movable locking ear. The frame comprises a first recess, a second recess opposite to the first recess, and a side wall between the first recess and the second recess. The movable locking ear comprises a first fastening member for fastening the first recess, a second fastening member opposite to the second fastening member for fastening the second recess, and a resisting member between the first fastening member and the second fastening member. A position of a bending end of the resisting member is near or far from the side wall depending on a distance between the first fastening member and the second fastening member.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: Various implementations disclosed herein include devices, systems, and methods that refine a first 3D surface representation (e.g., a 3D point cloud or a 3D mesh) using a second 3D surface representation that includes a 3D geometric primitive. In some implementations, a first 3D surface representation of a physical environment is obtained including points at 3D locations determined based on data generated by a first sensor. In some implementations, a second 3D surface representation corresponding to at least a portion of the physical environment is obtained that includes at least one 3D geometric primitive. In some implementations, a determination whether to adjust the 3D locations of at least one point of the points of the first 3D surface representation is made based on the 3D geometric primitive, and the 3D locations of the at least one point is adjusted to align with the geometric primitive based on the determination.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.