Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.

Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.

Abstract: The present disclosure provides a memory device and the forming method thereof. The memory device includes a gate structure on a substrate, a source/drain region in a substrate, a dielectric layer covering the substrate and the gate structure, and a cell contact adjacent to the gate structure. The cell contact includes a conductive layer, a first barrier layer on a sidewall of the conductive layer, and a second barrier layer on a bottom surface of the conductive layer. The second barrier layer directly contacts the first barrier layer and the source/drain region. A second resistivity of the second barrier layer is lower than a first resistivity of the first barrier layer.

Abstract: A window blind includes a headrail, two lift cords, a blind body, a bottom rail and two cord winding devices. The two cord winding devices are respectively installed on the bottom of the bottom rail. Subject to the technical feature that the opposite ends of the two lift cords are respectively tied to the adjustment columns of the two cord winding devices, if the winding stroke is inconsistent and the blind body is folded unevenly or skewed when the window blind is folded or stretched, the adjustment column of one cord winding device can be fine-adjusted to let the respective lift cord be gradually wound and covered on the adjustment column, so that the bottom rail and the blind body can be gradually adjusted to be substantially parallel to the bottom of the headrail, thereby effectively achieving the effect of fine-tuning and correcting the blind body.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

Abstract: The present disclosure provides an apparatus and a method for polishing a semiconductor substrate in semiconductor device manufacturing. The apparatus can include: a carrier configured to hold the substrate; a polishing pad configured to polish a first surface of the substrate; a chemical mechanical polishing (CMP) slurry delivery arm configured to dispense a CMP slurry onto the first surface of the substrate; and a pad conditioner configured to condition the polishing pad. In some embodiments, the pad conditioner can include: a conditioning disk configured to scratch the polishing pad; a conditioning arm configured to rotate the conditioning disk; a plurality of magnetic screws configured to secure the conditioning disk onto the conditioning arm and including a respective plurality of screw heads; and a plurality of blocking devices respectively positioned beneath the plurality of screw heads and configured to block debris particles from entering a respective plurality of screw holes.

Abstract: This document describes radar tracking with model estimates augmented by radar detections. An example tracker analyzes information derived using radar detections to enhance radar tracks having object measurements estimated from directly analyzing data cubes with a model (e.g., a machine-learning model). High-quality tracks with measurements to objects of importance can be quickly produced with the model. However, the model only estimates measurements for classes of objects its training or programming can recognize. To improve estimated measurements from the model, or even in some cases, to convey additional classes of objects, the tracker separately analyzes detections. Detections that consistently align to objects recognized by the model can update model-derived measurements conveyed initially in the tracks. Consistently observed detections that do not align to existing tracks may be used to establish new tracks for conveying more classes of objects than the model can recognize.