SILICON CARBIDE SEMICONDUCTOR DEVICE

Abstract

A gate insulating film is provided on a trench. The gate insulating film has a trench insulating film and a bottom insulating film. The trench insulating film covers each of a side wall and a bottom portion. The bottom insulating film is provided on the bottom portion with a trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is in contact with a portion of the trench insulating film on the side wall. Accordingly, a low threshold voltage and a large breakdown voltage can be attained.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a silicon carbide semiconductor device, in particular, a silicon carbide semiconductor device having a trench.

2. Description of the Background Art

Japanese Patent Laying-Open No. 7-326755 discloses a trench gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing a silicon carbide substrate. This patent publication describes that a gate thermal oxidation film has a thicker film thickness on a bottom surface of a trench than the film thickness thereof on a side surface of the trench, so that a threshold voltage becomes low and breakdown voltage between the gate and the drain becomes high. It is also described that the bottom surface of the trench corresponds to a carbon plane, which allows for fast oxidation rate, of hexagonal single-crystal silicon carbide, whereas the side surface of the trench corresponds to a plane perpendicular to this carbon plane and allowing for slow oxidation rate. Hence, by performing a thermal oxidation process once, a thermal oxidation film can be formed such that the thickness of the thermal oxidation film on the side surface of the trench is greatly different from the thickness of the thermal oxidation film on the bottom surface of the trench.

According to the technique of the above-described patent publication, the gate insulating film on the trench is entirely formed by the thermal oxidation on the trench of the silicon carbide substrate. The silicon carbide substrate used here normally has a high crystallinity, so that a thin and flat gate insulating film can be formed. In this way, low threshold voltage can be attained. However, in the insulating film thus formed by the thermal oxidation of silicon carbide, carbon atoms, which have existed in the silicon carbide, remains to an extent that cannot be disregarded. According to a study conducted by the present inventors, the carbon atoms remaining in the gate oxide film decrease dielectric breakdown resistance of the gate insulating film. Accordingly, it is considered that there is room for further improvement for the dielectric breakdown resistance in the above-described conventional technique. Namely, it is considered that there is room for further increasing the breakdown voltage of the silicon carbide semiconductor device.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problem and has its object to provide a silicon carbide semiconductor device having a low threshold voltage and a large breakdown voltage.

A silicon carbide semiconductor device of the present invention includes: a silicon carbide substrate, a gate insulating film, and a gate electrode. The silicon carbide substrate includes first to third layers. The first layer has first conductivity type. The second layer is provided on the first layer and has second conductivity type. The third layer is provided on the second layer, is separated from the first layer by the second layer, and has the first conductivity type. The silicon carbide substrate is provided with a trench. The trench includes a side wall and a bottom portion, the side wall extending through the third layer and the second layer and reaching the first layer, the bottom portion being formed of the first layer. The gate insulating film is provided on the trench. The gate insulating film includes a trench insulating film and a bottom insulating film. The trench insulating film covers each of the side wall and the bottom portion. The bottom insulating film is provided on the bottom portion with the trench insulating film being interposed therebetween. The bottom insulating film has a carbon atom concentration lower than that of the trench insulating film. The gate electrode is provided in the trench. The gate electrode is in contact with a portion of the trench insulating film on the side wall.

According to this silicon carbide semiconductor device, electric insulation between the gate electrode and the bottom portion of the trench is secured by the bottom insulating film in addition to the trench insulating film. With the low carbon atom concentration, the bottom insulating film has a high dielectric breakdown resistance. Accordingly, the silicon carbide semiconductor device has a large breakdown voltage. Further, according to the silicon carbide semiconductor device, the gate electrode is in contact with the portion of the trench insulating film on the side wall. Namely, the gate electrode faces the side wall that forms a channel, without the bottom insulating film being interposed therebetween. Thus, the bottom insulating film is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of the bottom insulating film.

Preferably, a total of a thickness of the trench insulating film on the bottom portion and a thickness of the bottom insulating film is larger than a thickness of the trench insulating film on the side wall. Accordingly, the thickness of the gate insulating film can be made small on the side wall whereas the thickness thereof can be made large on the bottom portion. Accordingly, the breakdown voltage of the silicon carbide semiconductor device can be made larger while making the threshold voltage small.

Preferably, on the bottom portion, a thickness of the bottom insulating film is larger than that of the trench insulating film. Accordingly, a ratio of the portion formed of the bottom insulating film of the gate insulating film is made large on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, a thickness of the trench insulating film on the bottom portion is smaller than a thickness of the trench insulating film on the side wall. Accordingly, a region for providing the bottom insulating film is further secured on the bottom portion. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, the carbon atom concentration of the trench insulating film is more than 1×10¹⁵ cm⁻³, and the carbon atom concentration of the bottom insulating film is less than 1×10¹⁵ cm⁻³. Accordingly, the carbon atom concentration in the bottom insulating film is sufficiently made low. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, the bottom insulating film has a thickness of more than 100 nm. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, the trench insulating film is a thermal oxidation film of silicon carbide. This makes the trench insulating film thin and smooth. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, the bottom insulating film is formed of at least any one of silicon oxide, silicon nitride, and phosphorus silicate glass. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

Preferably, the bottom insulating film is a thermal oxidation film of a film containing silicon and containing no carbon. This leads to a larger breakdown voltage of the silicon carbide semiconductor device.

As described above, according to the present invention, a low threshold voltage and a large breakdown voltage are attained.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a first embodiment of the present invention.

FIG. 2 is a perspective view schematically showing a shape of a silicon carbide substrate included in the silicon carbide semiconductor device of FIG. 1.

FIG. 3 shows the configuration of FIG. 2 more in detail with a region of second conductivity type being provided with hatching for viewability of the figure.

FIG. 4 is an enlarged view of FIG. 1.

FIG. 5 is a graph showing a profile of a carbon atom concentration along an arrow Z in FIG. 4.

FIG. 6 is a partial cross sectional view schematically showing a first step of a method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 7 is a partial cross sectional view schematically showing a second step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 8 is a partial cross sectional view schematically showing a third step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 9 is a partial cross sectional view schematically showing a fourth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 10 is a partial cross sectional view schematically showing a fifth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 11 is a partial cross sectional view schematically showing a sixth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 12 is a partial cross sectional view schematically showing a seventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 13 is a partial cross sectional view schematically showing an eighth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 14 is a partial cross sectional view schematically showing a ninth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 15 is a partial cross sectional view schematically showing a tenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 16 is a partial cross sectional view schematically showing an eleventh step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 17 is a partial cross sectional view schematically showing a twelfth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 18 is a partial cross sectional view schematically showing a thirteenth step of the method for manufacturing the silicon carbide semiconductor device of FIG. 1.

FIG. 19 is a partial cross sectional view schematically showing one step of a method for manufacturing a silicon carbide semiconductor device of a comparative example.

FIG. 20 is a partial cross sectional view schematically showing a configuration of a silicon carbide semiconductor device in a second embodiment of the present invention.

FIG. 21 is a partial cross sectional view schematically showing a fine structure in a surface of a silicon carbide substrate included in the silicon carbide semiconductor device.

FIG. 22 shows a crystal structure of a (000-1) plane in a hexagonal crystal of polytype 4H.

FIG. 23 shows a crystal structure of a (11-20) plane along a line XXIII-XXIII in FIG. 22.

FIG. 24 shows a crystal structure of a combined plane of FIG. 21 in the vicinity of the surface within the (11-20) plane.

FIG. 25 shows the combined plane of FIG. 21 when viewed from a (01-10) plane.

FIG. 26 is a graph showing an exemplary relation between channel mobility and an angle between a channel surface and the (000-1) plane when macroscopically viewed, in each of a case where thermal etching is performed and a case where no thermal etching is performed.

FIG. 27 is a graph showing an exemplary relation between the channel mobility and an angle between a channel direction and a <0-11-2> direction.

FIG. 28 shows a modification of FIG. 21.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes embodiments of the present invention based on figures. It should be noted that in the below-mentioned figures, the same or corresponding portions are given the same reference characters and are not described repeatedly. Regarding crystallographic indications in the present specification, an individual orientation is represented by [ ], a group orientation is represented by < >, and an individual plane is represented by ( ) and a group plane is represented by { }. In addition, a negative crystallographic index is normally expressed by putting “-” (bar) above a numeral, but is expressed by putting the negative sign before the numeral in the present specification.

First Embodiment

As shown in FIG. 1, a vertical type MOSFET 500 (silicon carbide semiconductor device) of the present embodiment includes an epitaxial substrate 100 (silicon carbide substrate), gate insulating films 201, gate electrodes 202, interlayer insulating films 203, source electrodes 221, a drain electrode 211, a source interconnection 222, and a protecting electrode 212.

Epitaxial substrate 100 is made of silicon carbide, and has a single-crystal substrate 110 and an epitaxial layer provided thereon. The epitaxial layer includes an n⁻layer 121 (first layer), p type body layers 122 (second layer), n regions 123 (third layer), and contact regions 124. The silicon carbide of epitaxial substrate 100 preferably has a hexagonal crystal structure, more preferably, has a polytype of 4H.

Single-crystal substrate 110 has n type (first conductivity type) conductivity. The plane orientation (hklm) of one main surface (upper surface in FIG. 1) of single-crystal substrate 110 preferably has m of negative value, more preferably, corresponds to approximately a (000-1) plane.

N⁻layer 121 has a donor added therein and therefore has n type conductivity. The donor is preferably added to n⁻layer 121 by adding an impurity during epitaxial growth of n⁻layer 121, rather than ion implantation. N⁻layer 121 preferably has a donor concentration lower than that of single-crystal substrate 110. N⁻layer 121 preferably has a donor concentration of not less than 1×10¹⁵ cm⁻³ and not more than 5×10¹⁶ cm⁻³, for example, has a donor concentration of 8×10¹⁵ cm⁻³.

Each of p type body layers 122 is provided on n⁻layer 121, has an acceptor added therein, and therefore has p type conductivity (second conductivity type). P type body layer 122 has an acceptor concentration of, for example, 1×10¹⁸ cm⁻³.

Each of n regions 123 has n type conductivity. N region 123 is provided on p type body layer 122, and is separated from n layer 121 by p type body layer 122. Contact region 124 has p type conductivity. Contact region 124 is formed on a portion of p type body layer 122 so as to be connected to p type body layer 122.

Further, referring to FIG. 2 and FIG. 3, epitaxial substrate 100 is provided with a trench TR. Trench TR has side walls SW and a bottom portion BT. Each of side walls SW extends through n region 123 and p type body layer 122 and reaches n layer 121. Bottom portion BT is formed of n layer 121. Side wall SW has a channel surface CH on p type body layer 122 (FIG. 3). Bottom portion BT is a flat surface substantially parallel to the main surface of epitaxial substrate 100. Preferably, side wall SW has a predetermined crystal plane (also referred to as “special plane”) particularly on p type body layer 122. Details of the special plane will be described later.

The fact that epitaxial substrate 100 has trench TR corresponds to such a fact that the epitaxial layer is partially removed above the upper surface of single-crystal substrate 110. In the present embodiment, a multiplicity of mesa structures are formed on the upper surface of single-crystal substrate 110. Specifically, each of the mesa structures has upper surface and bottom portion both having a hexagonal shape, and has side walls inclined relative to the main surface of single-crystal substrate 110. Thus, trench TR expands toward the opening in a tapering manner.

Gate insulating film 201 is provided on trench TR. Gate insulating film 201 separates epitaxial substrate 100 and gate electrode 202 from each other in trench TR. Gate insulating film 201 has a trench insulating film 201A and a bottom insulating film 201B. Trench insulating film 201A covers each of side walls SW and bottom portion BT. Bottom insulating film 201B is provided on bottom portion BT with trench insulating film 201A being interposed therebetween. Bottom insulating film 201B has a portion located at a corner portion formed by bottom portion BT and each side wall SW.

Bottom insulating film 201B has a carbon atom concentration lower than that of trench insulating film 201A. Preferably, trench insulating film 201A is a thermal oxidation film of silicon carbide. In this case, trench insulating film 201A is made of silicon oxide containing carbon atoms as an impurity. Preferably, bottom insulating film 201B is a thermal oxidation film of a film containing silicon and containing no carbon. In the present embodiment, bottom insulating film 201B is a thermal oxidation film of a silicon film, and is made of silicon oxide.

As shown in FIG. 4, trench insulating film 201A has a thickness t1 on side wall SW and has a thickness t2 on bottom portion BT. Bottom insulating film 201B has a thickness t3 on bottom portion BT. Preferably, a total of thickness t2 and thickness t3 is larger than thickness t1. Preferably, thickness t3 is larger than thickness t2. Preferably, thickness t2 is smaller than thickness t1. Preferably, thickness t3 is larger than 100 nm.

Trench insulating film 201A may have a carbon atom concentration of more than 1×10¹⁵ cm⁻³. Bottom insulating film 201B preferably has a carbon atom concentration of less than 1×10¹⁵ cm⁻³. It should be noted that in the case where the carbon atom concentrations are not uniform, an average value may be calculated.

Further, referring to FIG. 5, a solid line of FIG. 5 illustrates a profile of a carbon atom concentration NC in the thickness direction (arrow Z in FIG. 4) from the bottom portion BT toward the trench. A location Z=0 corresponds to an interface between bottom portion BT and trench insulating film 201A. A location Z=t2 corresponds to an interface between trench insulating film 201A and bottom insulating film 201B. A location Z=t2+t3 corresponds to an interface between bottom insulating film 201B and gate electrode 202. When 0≦z≦t2, carbon atom concentration NC becomes smaller as Z increases. In the vicinity of Z=0 (arrow d1 in the figure), the decrease of carbon atom concentration NC is relatively gradual. When Z>t2, carbon atom concentration NC substantially reaches or falls below the detection limit. In the vicinity of location Z=0, trench insulating film 201A typically has a carbon atom concentration NC of more than approximately 1×10¹⁷ cm⁻³ and less than approximately 1×10²⁰ cm⁻³, for example, has a carbon atom concentration NC of approximately 1×10¹⁸ cm⁻³.

Gate electrode 202 is provided in trench TR. Specifically, gate electrode 202 is buried in trench TR with gate insulating film 201 interposed therebetween. Gate electrode 202 is in contact with trench insulating film 201A at a portion located on side wall SW. On side wall SW, gate electrode 202 faces the surface of p type body layer 122 with only trench insulating film 201A being interposed therebetween. In other words, bottom insulating film 201B is not provided between the portion of trench insulating film 201A on side wall SW and gate electrode 202. Gate electrode 202 has an upper surface substantially as high as the upper surface of a portion of gate insulating film 201 on the upper surface of n region 123. Interlayer insulating film 203 is provided to cover gate electrode 202 as well as the extended portion of gate insulating film 201 on the upper surface of n region 123.

Source electrode 221 extends through interlayer insulating film 203 and makes contact with each of n regions 123 and contact region 124. Source interconnection 222 is provided on source electrode 221 and interlayer insulating film 203 in contact with source electrode 221. Drain electrode 211 is provided on an opposite surface of epitaxial substrate 100 to its surface in which trench TR is provided. Protecting electrode 212 covers drain electrode 211.

The following describes a method for manufacturing MOSFET 500 (FIG. 1).

As shown in FIG. 6, on single-crystal substrate 110, n⁻layer 121 is formed by means of epitaxial growth. This epitaxial growth can be performed by means of, for example, a CVD (Chemical Vapor Deposition) method in which a mixed gas of silane (SiH₄) and propane (C₃H₈) is used as a source material gas and hydrogen gas (H₂) is used as a carrier gas, for example. In doing so, it is preferable to introduce nitrogen (N) or phosphorus (P) as a donor, for example.

As shown in FIG. 7, p type body layer 122 is formed on n′ layer 121, and n region 123 is formed on p type body layer 122. Specifically, ion implantation is performed into the upper surface of n⁻layer 121. In the ion implantation for forming p type body layer 122, ions of an acceptor such as aluminum (Al) are implanted. Meanwhile, in the ion implantation for forming n region 123, ions of a donor such as phosphorus (P) are implanted, for example. Accordingly, epitaxial substrate 100 is formed which has n⁻layer 121, p type body layer 122, and n region 123. It should be noted that instead of the ion implantation, epitaxial growth involving addition of impurities may be employed.

As shown in FIG. 8, by means of the ion implantation, contact regions 124 are formed. Next, activation heating treatment is performed to activate the impurities added by the ion implantation. This heat treatment is preferably performed at a temperature of not less than 1500° C. and not more than 1900° C., for example, a temperature of approximately 1700° C. The heat treatment is performed for approximately 30 minutes, for example. The atmosphere of the heat treatment is preferably an inert gas atmosphere, such as Ar atmosphere.

Next, a mask 247 (FIG. 9) having an opening through which n region 123 is partially exposed is formed on epitaxial substrate 100. The opening is formed to correspond to the location of trench TR (FIG. 1). As mask 247, a silicon oxide film formed through thermal oxidation can be used, for example.

As shown in FIG. 10, in the opening of mask 247, n region 123, p type body layer 122, and a portion of n⁻layer 121 are removed by etching. An exemplary, usable etching method is reactive ion etching (RIB), in particular, inductively coupled plasma (ICP) RIE. Specifically, ICP-RIE can be employed in which SF₆ or a mixed gas of SF₆ and O₂ is used as the reactive gas, for example. By means of such etching, in the region where trench TR (FIG. 1) is to be formed, a recess TQ can be formed which has a side wall having an inner surface SV substantially perpendicular to the main surface of single-crystal substrate 110.

Next, using mask 247, epitaxial substrate 100 is etched. Specifically, inner surface SV of recess TQ of epitaxial substrate 100 is thermally etched. The thermal etching can be performed by, for example, heating epitaxial substrate 100 in an atmosphere including a reactive gas containing at least one or more types of halogen atom. The at least one or more types of halogen atom include at least one of chlorine (Cl) atom and fluorine (F) atom. This atmosphere is, for example, Cl₂, BCL₃, SF₆, or CF₄. For example, the thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reactive gas, at a heat treatment temperature of, for example, not less than 700° C. and not more than 1000° C.

As a result of the thermal etching, trench TR is formed as shown in FIG. 11. During the formation of trench TR, epitaxial substrate 100 is etched in a side etching manner from the opening of mask 247 as indicated by an arrow SE. Further, during this thermal etching, a special plane is spontaneously formed in side wall SW of trench TR, in particular, its portion formed of p type body layer 122.

It should be noted that the reactive gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas. An exemplary, usable carrier gas is nitrogen (N₂) gas, argon gas, helium gas, or the like. When the heat treatment temperature is set at not less than 700° C. and not more than 1000° C. as described above, a rate of etching SiC is approximately, for example, 70 μm/hour. In addition, in this case, mask 247, which is formed of silicon oxide and therefore has a very large selection ratio relative to SiC, is not substantially etched during the etching of SiC.

As shown in FIG. 12, a silicon film 90 is formed on epitaxial substrate 100 having mask 247 provided thereon. In other words, silicon film 90 is formed while using mask 247. Silicon film 90 is formed on bottom portion BT of trench TR. This formation can be performed by means of, for example, the CVD method. Next, mask 247 is removed by means of an appropriate method such as etching (FIG. 13). In doing so, the portion of silicon film 90 on mask 247 is also removed.

Next, oxidation is performed in trench TR, thereby forming gate insulating film 201 (FIG. 1) on trench TR. Specifically, the following steps are performed. First, silicon film 90 (FIG. 13) is thermally oxidized. Accordingly, an silicon oxide film is formed (FIG. 14) which serves as bottom insulating film 201B that forms a portion of gate insulating film 201 (FIG. 1). Silicon film 90 is thermally oxidized at, for example, not less than 800° C. and not more than 950° C. Next, as shown in FIG. 15, epitaxial substrate 100 made of silicon carbide is thermally oxidized, thereby forming an silicon oxide film serving as trench insulating film 201A of gate insulating film 201. Epitaxial substrate 100 is preferably thermally oxidized at a temperature higher than the temperature at which silicon film 90 is thermally oxidized, for example, is thermally oxidized at 1300° C. or more.

As shown in FIG. 16, gate electrode 202 is formed on gate insulating film 201. Gate electrode 202 is formed in direct contact with trench insulating film 201A on p type body layer 122. A method for forming gate electrode 202 can be performed by, for example, forming a film of conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing).

As shown in FIG. 17, interlayer insulating film 203 is formed on gate electrode 202 and gate insulating film 201 so as to cover the exposed surface of gate electrode 202. Referring to FIG. 18, etching is performed to form openings in interlayer insulating film 203 and gate insulating film 201. Through the opening, each of n region 123 and contact region 124 is exposed on the upper surface of the mesa structure. Next, on the upper surface of the mesa structure, source electrode 221 is formed in contact with each of n region 123 and contact region 124. Referring to FIG. 1 again, source interconnection 222, drain electrode 211, and protecting electrode 212 are formed. In this way, MOSFET 500 is obtained.

According to MOSFET 500 (FIG. 4) of the present embodiment, electric insulation between gate electrode 202 and bottom portion BT of trench TR is secured by bottom insulating film 201B in addition to trench insulating film 201A. Bottom insulating film 201B has a low carbon atom concentration, and therefore has a high dielectric breakdown resistance. Accordingly, MOSFET 500 has a large breakdown voltage. Further, according to this MOSFET 500, gate electrode 202 is in contact with the portion of trench insulating film 201A on side wall SW. Namely, gate electrode 202 faces side wall SW that forms a channel, without bottom insulating film 201B being interposed therebetween. Thus, bottom insulating film 201B is disposed so as not to increase the threshold voltage. Accordingly, a low threshold voltage is attained without influence of bottom insulating film 201B.

Further, trench insulating film 201A is a thermal oxidation film of silicon carbide of epitaxial substrate 100 (see FIG. 14 and FIG. 15). This makes the trench insulating film thin and smooth. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.

Further, bottom insulating film 201B is made of silicon oxide. In this way, the breakdown voltage of MOSFET 500 can be made larger. Further, bottom insulating film 201B is silicon film 90, i.e., a thermal oxidation film of a film containing silicon and containing no carbon. In this way, the breakdown voltage of MOSFET 500 can be made larger.

When t2+t3>t1, the thickness of gate insulating film 201 can be made small on side wall SW whereas the thickness thereof can be made large on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger while making the threshold voltage small.

When t3>t2, a ratio of the portion formed of bottom insulating film 201B of gate insulating film 201 becomes large on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.

When t2<t1, a region for providing bottom insulating film 201B is further secured on bottom portion BT. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.

When t3>100 nm, the breakdown voltage of MOSFET 500 can be made larger.

When bottom insulating film 201B has a carbon atom concentration of less than 1×10¹⁵ cm⁻³, the carbon atom concentration of bottom insulating film 201B is sufficiently low. Accordingly, the breakdown voltage of MOSFET 500 can be made larger.

Further, according to the present embodiment, the decrease of carbon atom concentration NC in gate insulating film 201 just above bottom portion BT of trench TR (FIG. 5) is relatively gradual as indicated by arrow d1 (FIG. 5). Accordingly, generation of stress due to the composition change in gate insulating film 201 can be suppressed. In contrast, if a gate insulating film 201Z is formed by means of thermal oxidation of epitaxial substrate 100 without bottom insulating film 201B (FIG. 15) as shown in FIG. 19, carbon atom concentration NC is drastically decreased in gate insulating film 201Z just above bottom portion BT of trench TR as indicated by arrow d2 (FIG. 5). As a result, stress is likely to be applied to gate insulating film 201Z.

It should be noted that in the present embodiment, the silicon oxide film serving as bottom insulating film 201B (FIG. 14) is a silicon oxide film formed through the thermal oxidation of silicon film 90 (FIG. 13), but the silicon oxide film may be formed through, for example, the CVD method instead of forming silicon film 90. Further, the material of the bottom insulating film is not limited to silicon oxide, and may be phosphorus silicate glass or silicon nitride, for example. A film made of silicon nitride can be formed by means of, for example, the CVD method.

Further, the “first conductivity type” corresponds to n type conductivity, and the “second conductivity type” corresponds to p type conductivity, but these conductivity types may be replaced with each other. In this case, the donor and acceptor in the foregoing description are also replaced with each other. It should be noted that in order to attain higher channel mobility, it is preferable that the “first conductivity type” corresponds to n type conductivity. Further, the silicon carbide semiconductor device is not limited to the MOSFET, and may be a trench type IGBT (Insulated Gate Bipolar Transistor), for example.

Second Embodiment

As shown in FIG. 20, a MOSFET 500v (silicon carbide semiconductor device) of the present embodiment has a trench TRv having a V shape instead of trench TR (FIG. 4). Trench TRv has a bottom portion BTv, instead of bottom portion BT (FIG. 4). When viewed in cross section (FIG. 20), bottom portion BTv is a portion in which side walls SW facing each other make contact with each other so as to form a V shape. Apart from the configuration described above, the configuration of the present embodiment is substantially the same as the configuration of the first embodiment. Hence, the same or corresponding elements are given the same reference characters and are not described repeatedly.

(Surface Having Special Plane)

As described above, side wall SW (FIG. 1) of trench TR preferably has a predetermined crystal plane (also referred to as “special plane”) on, in particular, p type body layer 122. Such a side wall SW includes a plane S1 (first plane) having a plane orientation of {0-33-8} as shown in FIG. 21. Plane S1 preferably has a plane orientation of (0-33-8).

More preferably, side wall SW microscopically includes plane S1, and side wall SW microscopically further includes a plane S2 (second plane) having a plane orientation of {0-11-1}. Here, the term “microscopically” refers to “minutely to such an extent that at least the size about twice as large as an interatomic spacing is considered”. As a method for observing such a microscopic structure, for example, a TEM (Transmission Electron Microscope) can be used. Preferably, plane S2 has a plane orientation of (0-11-1).

Preferably, plane S1 and plane S2 of side wall SW forms a combined plane SR having a plane orientation of {0-11-2}. Specifically, combined plane SR is formed of periodically repeated planes S1 and S2. Such a periodic structure can be observed by, for example, TEM or AFM (Atomic Force Microscopy). In this case, combined plane SR has an off angle of 62° relative to the {000-1} plane, macroscopically. Here, the term “macroscopically” refers to “disregarding a fine structure having a size of approximately interatomic spacing”. For the measurement of such a macroscopic off angle, a method employing general X-ray diffraction can be used, for example. Preferably, combined plane SR has a plane orientation of (0-11-2). In this case, combined plane SR has an off angle of 62° relative to the (000-1) plane, macroscopically.

Preferably, in the channel surface, carriers flow in a channel direction CD, in which the above-described periodic repetition is done.

The following describes detailed structure of combined plane SR.

Generally, regarding Si atoms (or C atoms), when viewing a silicon carbide single-crystal of polytype 4H from the (000-1) plane, atoms in a layer A (solid line in the figure), atoms in a layer B (broken line in the figure) disposed therebelow, and atoms in a layer C (chain line in the figure) disposed therebelow, and atoms in a layer B (not shown in the figure) disposed therebelow are repeatedly provided as shown in FIG. 22. In other words, with four layers ABCB being regarded as one period, a periodic stacking structure such as ABCBABCBABCB . . . is provided.

As shown in FIG. 23, in the (11-20) plane (cross section taken along a line XXIII-XXIII of FIG. 22), atoms in each of four layers ABCB constituting the above-described one period are not aligned completely along the (0-11-2) plane. In FIG. 23, the (0-11-2) plane is illustrated to pass through the locations of the atoms in layers B. In this case, it is understood that each of atoms in layers A and C is deviated from the (0-11-2) plane. Hence, even when the macroscopic plane orientation of the surface of the silicon carbide single-crystal, i.e., the plane orientation thereof with its atomic level structure being ignored is limited to (0-11-2), this surface can have various structures microscopically.

As shown in FIG. 24, combined plane SR is constructed by alternately providing planes S1 having a plane orientation of (0-33-8) and planes S2 connected to planes S1 and having a plane orientation different from that of each of planes S1. Each of planes S1 and S2 has a length twice as large as the interatomic spacing of the Si atoms (or C atoms). It should be noted that a plane with plane S1 and plane S2 being averaged corresponds to the (0-11-2) plane (FIG. 23).

As shown in FIG. 25, when viewing combined plane SR from the (01-10) plane, the single-crystal structure has a portion periodically including a structure (plane S1 portion) equivalent to a cubic structure. Specifically, combined plane SR is constructed by alternately providing planes S1 having a plane orientation of (001) in the above-described structure equivalent to the cubic structure and planes S2 connected to planes S1 and having a plane orientation different from that of each of planes S1. Also in a polytype other than 4H, the surface can be formed of the planes (planes S1 in FIG. 25) having a plane orientation of (001) in the structure equivalent to the cubic structure and the planes (planes S2 in FIG. 25) connected to the foregoing planes and having a plane orientation different from that of each of the foregoing planes. The polytype may be, for example, 6H or 15R.

Referring to FIG. 26, the following describes a relation between the crystal plane of side wall SW and mobility MB of the channel surface. In the graph of FIG. 26, the horizontal axis represents an angle D1 formed by the (000-1) plane and the macroscopic plane orientation of side wall SW having the channel surface, whereas the vertical axis represents mobility MB. A group of plots CM correspond to a case where side wall SW is finished to correspond to a special plane by thermal etching, whereas a group of plots MC correspond to a case where side wall SW is not thermally etched.

In group of plots MC, mobility MB is at maximum when the surface of the channel surface has a macroscopic plane orientation of (0-33-8). This is presumably due to the following reason. That is, in the case where the thermal etching is not performed, i.e., in the case where the microscopic structure of the channel surface is not particularly controlled, the macroscopic plane orientation thereof corresponds to (0-33-8), with the result that a ratio of the microscopic plane orientation of (0-33-8), i.e., the plane orientation of (0-33-8) in consideration of that in atomic level becomes statistically high.

On the other hand, mobility MB in group of plots CM is at maximum when the macroscopic plane orientation of the channel surface is (0-11-2) (arrow EX). This is presumably due to the following reason. That is, as shown in FIG. 24 and FIG. 25, the multiplicity of planes S1 each having a plane orientation of (0-33-8) are densely and regularly arranged with planes S2 interposed therebetween, whereby a ratio of the microscopic plane orientation of (0-33-8) becomes high in the surface of the channel surface.

It should be noted that mobility MB has orientation dependency on combined plane SR. In a graph shown in FIG. 27, the horizontal axis represents an angle D2 between the channel direction and the <0-11-2> direction, whereas the vertical axis represents mobility MB (in any unit) in the channel surface. A broken line is supplementarily provided therein for viewability of the graph. From this graph, it has been found that in order to increase channel mobility MB, channel direction CD (FIG. 21) preferably has an angle D2 of not less than 0° and not more than 60°, more preferably, substantially 0°.

As shown in FIG. 28, side wall SW may further include plane S3 (third plane) in addition to combined plane SR. More specifically, side wall SW may include a combined plane SQ formed of periodically repeated plane S3 and combined plane SR. In this case, the off angle of side wall SW relative to the {000-1} plane is deviated from the ideal off angle of combined plane SR, i.e., 62°. Preferably, this deviation is small, preferably, in a range of ±10°. Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the {0-33-8} plane. More preferably, the off angle of side wall SW relative to the (000-1) plane is deviated from the ideal off angle of combined plane SR, i.e., 62°. Preferably, this deviation is small, preferably, in a range of ±10°. Examples of a surface included in such an angle range include a surface having a macroscopic plane orientation of the (0-33-8) plane.

Such a periodic structure can be observed by, for example, TEM or AFM. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.

Claims

1. A silicon carbide semiconductor device comprising:

a silicon carbide substrate including a first layer having first conductivity type, a second layer provided on said first layer and having second conductivity type, and a third layer provided on said second layer, separated from said first layer by said second layer, and having said first conductivity type, said silicon carbide substrate being provided with a trench having a side wall and a bottom portion, said side wall extending through said third layer and said second layer and reaching said first layer, said bottom portion being formed of said first layer;

a gate insulating film provided on said trench, said gate insulating film including a trench insulating film and a bottom insulating film, said trench insulating film covering each of said side wall and said bottom portion, said bottom insulating film being provided on said bottom portion with said trench insulating film being interposed therebetween, said bottom insulating film having a carbon atom concentration lower than that of said trench insulating film; and

a gate electrode provided in said trench, said gate electrode being in contact with a portion of said trench insulating film on said side wall.

2. The silicon carbide semiconductor device according to claim 1, wherein a total of a thickness of said trench insulating film on said bottom portion and a thickness of said bottom insulating film is larger than a thickness of said trench insulating film on said side wall.

3. The silicon carbide semiconductor device according to claim 1, wherein on said bottom portion, a thickness of said bottom insulating film is larger than that of said trench insulating film.

4. The silicon carbide semiconductor device according to claim 1, wherein a thickness of said trench insulating film on said bottom portion is smaller than a thickness of said trench insulating film on said side wall.

5. The silicon carbide semiconductor device according to claim 1, wherein the carbon atom concentration of said trench insulating film is more than 1×1015 cm−3, and the carbon atom concentration of said bottom insulating film is less than 1×1015 cm−3.

6. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film has a thickness of more than 100 nm.

7. The silicon carbide semiconductor device according to claim 1, wherein said trench insulating film is a thermal oxidation film of silicon carbide.

8. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film is formed of at least any one of silicon oxide, silicon nitride, and phosphorus silicate glass.

9. The silicon carbide semiconductor device according to claim 1, wherein said bottom insulating film is a thermal oxidation film of a film containing silicon and containing no carbon.