Abstract: Techniques and implementations related to automatic image capture during preview, as well as recommendation of images, are described. A method for operating an electronic apparatus may involve receiving a stream of one or more preview images in a preview mode of the electronic apparatus. The method may also involve determining whether any preview image of the stream of preview images is valuable. The method may further involve controlling an operation of the electronic apparatus in response to the determining.

Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.

Abstract: A light emitting chip operating under a DC power supply is provided. The light emitting chip includes a substrate and a plurality of light emitting elements. The light emitting elements are arranged on the substrate, and have the same or different area sizes. The light emitting elements are driven by a single driving voltage or sectionally driven by a plurality of driving voltages.

Abstract: A spin-dryer includes an external drum, an internal drum and a spinning unit. The external drum includes a containing chamber. The internal drum is rotationally inserted in the containing chamber. The internal drum includes a spinning chamber, apertures in communication with the spinning chamber, and a lower axle rotationally inserted in the external drum. The spinning unit includes a motor inserted in the external drum, a driver gear operatively connected to the motor, and a follower gear connected to the lower axle and engaged with the driver gear.

Abstract: A pair of glasses has a glasses body and an adjusting structure. The glasses body has a lens frame and a nose pad. The nose pad is combined with the lens frame by two sliding slices and two tracks. The adjusting structure is mounted between the lens frame and the nose pad and has a first engaging block, a second engaging block, and a stopping block. The first engaging block and the second engaging block can be engaged with each other to keep the nose pad from separating from the lens frame. The stopping block is mounted to form a friction between the nose pad and the lens frame. The nose pad can be precisely adjusted and fine-tuned relative to the lens frame because of the sliding slices, the tracks, and the stopping block.

Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract: A pair of glasses has a glasses body and an adjusting structure. The glasses body has a lens frame and a nose pad. The nose pad is combined with the lens frame by two sliding slices and two tracks. The adjusting structure is mounted between the lens frame and the nose pad and has a first engaging block, a second engaging block, and a stopping block. The first engaging block and the second engaging block can be engaged with each other to keep the nose pad from separating from the lens frame. The stopping block is mounted to form a friction between the nose pad and the lens frame. The nose pad can be precisely adjusted and fine-tuned relative to the lens frame because of the sliding slices, the tracks, and the stopping block.

Abstract: A display module includes a transparent substrate, a black matrix layer, several light-shielding elements and a phase retardation film. The transparent substrate includes left-eye pixel regions and right-eye pixel regions for respectively displaying left-eye images and right-eye images. Each left-eye pixel region is adjacent to each right-eye pixel region. The black matrix layer is disposed on one side of the transparent substrate and corresponds to each boundary between the left-eye and right-eye pixel regions. The light-shielding elements are disposed on the other side of the transparent substrate and respectively correspond to the boundaries between the left-eye and right-eye pixel regions. The phase retardation film is disposed on the other side of the transparent substrate, and has first-phase retardation regions and second-phase retardation regions with difference phases.

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract: A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

Abstract: A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.

Abstract: A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.

Abstract: A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.

Abstract: A dual-band and dual polarization antenna includes a first baseboard and a second baseboard spacing apart from each other. A top surface of the first baseboard includes a first radiation part and a second radiation part. The second radiation part encloses the first radiation part and does not contact the first radiation part. The second baseboard includes a top surface facing the bottom surface of the first baseboard and a bottom surface. The top surface of the second baseboard includes a ground portion and two slot pairs each of which includes two slots. The two slots comprised in each slot pair are symmetrical to each other, and the symmetrical center of each slot pair aligns with the center of the first radiation part. The bottom surface includes a first microstrip line and a second microstrip line for feeding back wireless signals.

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract: A terminal circuit is applied to a bi-directional coupler. The terminal circuit includes a transmission line having a first end and a second end, a first resistor connecting the first end and a first ground and a second resistor connecting the second end and a second ground. A resistance value of the first resistor is substantially identical to that of the second resistor.

Abstract: A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.

Abstract: A light emitting chip operating under a DC power supply is provided. The light emitting chip includes a substrate and a plurality of light emitting elements. The light emitting elements are arranged on the substrate, and have the same or different area sizes. The light emitting elements are driven by a single driving voltage or sectionally driven by a plurality of driving voltages.