Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

Abstract: A connection interface adapted for die-to-die includes a plurality of first usage lanes, a plurality of first spare lanes, a plurality of receiving lanes, and a controller. The controller is configured to connect each of the plurality of receiving lanes to a corresponding one of the plurality of first usage lanes and to respectively monitor the plurality of first usage lanes. In response to that any of the plurality of first usage lanes is monitored as an unhealthy lane by the controller, the controller changes one of the plurality of receiving lanes which is currently connected to the unhealthy lane to be instead connected to one of the plurality of first spare lanes.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: A method of forming a semiconductor device includes: forming an opening in a dielectric layer to expose an underlying conductive feature; conformally forming a first protection layer and a second protection layer in the opening; performing an anisotropic etching to remove a first portion of the second protection layer from the bottom of the opening while keeping a second portion of the second protection layer along the sidewalls of the opening; after the anisotropic etching, performing an isotropic etching to remove, from the sidewalls of the opening, an upper portion and a lower portion of the first protection layer while keeping a middle portion of the first protection layer along the sidewalls of the opening; after the isotropic etching, performing an anneal to at least partially convert the second portion of the second protection layer into an oxide; and after the anneal, filling the opening with a conductive material.

Abstract: A portable electronic device including a main display having a locking recess at a side edge and at least one external display detachable relative to the side edge of the main display is provided. The external display includes a body, and at least one latch pivoted to the body. The latch is pivoted to the body to be swiveled out of or into the body. An opening of the locking recess faces obliquely upward and faces away from a direction of gravity when the main display is standing, the at least one latch swiveled out of the body faces obliquely downward and faces forward the direction of gravity to be inserted into the locking recess, and the at least one external display is hung on at the side edge of the main display by a weight of the at least one external display.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a rotating shaft fixed to the second body. When the second body rotates relative to the first body, the rotating shaft slides along an arc-shaped path to increase or decrease a distance between a lower edge of the second body and a back side of the first body.

Abstract: The invention provides an electronic package module including a chip, a heat-dissipation component, a carrying member, and a liquid metal. The carrying member is clamped between the chip and the heat-dissipation component. The carrying member has a porous structure. The liquid metal is filled in the porous structure to be in thermal contact with the chip and the heat-dissipation component. The liquid metal is constrained between the chip and the heat-dissipation component by the carrying member and does not flow outside of the chip and the heat-dissipation component.

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

Abstract: A hinge mechanism is provided, including a connecting unit, a hinge unit, and a locking element. The connecting unit has a connecting member and a tubular member. The tubular member is disposed on the connecting member. The hinge unit has a first member, a second member, a shaft, and a rod. The shaft pivotally connects the first member to the second member. The rod is affixed to the second member. The rod extends into the tubular member and has a slot. The locking element is fastened through the tubular member and joined in the slot.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor feature over a substrate, the semiconductor feature includes a conductive region; forming a dielectric layer over the semiconductor feature; patterning the dielectric layer to form a contact opening exposing a top surface of the conductive region; forming a monolayer over the dielectric layer, the top surface of the conductive region remaining exposed; and depositing a conductive material in the contact opening.

Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.