Patents by Inventor Yu-Shih Wang

Yu-Shih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327760
    Abstract: A method includes forming a dummy gate structure over a substrate; forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure; forming an interlayer dielectric (ILD) layer surrounding the gate spacers; replacing the dummy gate structure with a metal gate structure; etching back the metal gate structure to form a gate trench between the gate spacers; depositing a first dielectric layer in the gate trench, in which the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers; etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers exposed; and performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Jung HO, Yu-Shih WANG, Tze-Liang LEE
  • Patent number: 11146031
    Abstract: An expansion device includes a supporting base and a hub. The supporting base includes a bottom portion, a supporting portion, and an electrical connection port. The supporting portion is connected to the bottom portion and has an insert slot. The electrical connection port is disposed at the bottom portion. The hub is slidably disposed within the supporting portion and is located between the bottom portion and the insert slot. The hub includes a first electrical connection element and a second electrical connection element facing away from the first electrical connection element. The first electrical connection element is electrically connected to the electrical connection port, and the second electrical connection element extends into the insert slot. Another expansion device is also provided.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 12, 2021
    Assignee: Acer Incorporated
    Inventors: Ting-Wen Pai, Wen-Chieh Tai, Han-Tsung Shen, Yu-Shih Wang
  • Patent number: 11139011
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: October 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Publication number: 20210303096
    Abstract: A detection method of a three-dimensional touch module includes: step S1, providing an input signal to a transmitting electrode layer; step S2, outputting a first output signal and transmitting the first output signal to a control module by a two-dimensional inputting assembly, and outputting a second output signal and transmitting the second output signal to the control module by a pressure sensing assembly; and step S3, determining, by the control module, a touch position according to the first output signal and a pressure value according to the second output signal. A three-dimensional touch module includes: a cover plate; a two-dimensional inputting assembly disposed under the cover plate and configured to output a first output signal; a pressure sensing assembly disposed under the cover plate and configured to output a second output signal; and a transmitting electrode layer disposed between the two-dimensional inputting assembly and the pressure sensing assembly.
    Type: Application
    Filed: September 25, 2020
    Publication date: September 30, 2021
    Inventors: Cai Jin Ye, Chih-Cheng Chuang, Lien-Hsin Lee, Tsai-Kuei Wei, Sun Po Lin, Ren-Hung Wang, Yu-Ting Chan, Tai-Shih Cheng, Yan Zhao
  • Publication number: 20210296572
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20210223821
    Abstract: An electronic device assembly is provided, including an electronic device body and a detachable lens module. The electronic device body has a housing and a first joining unit, wherein the first joining unit is disposed on the housing. The detachable lens module is detachably assembled onto the housing and has a second joining unit, wherein the first joining unit is joined to the second joining unit to electrically connect the detachable lens module to the electronic device body.
    Type: Application
    Filed: June 19, 2020
    Publication date: July 22, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Yi-Ta Huang, Chih-Chun Liu, Cheng-Nan Ling, Wen-Chieh Tai, Chi-Hung Lai, Wu-Chen Lee, Pin-Chueh Lin, Chih-Wei Liao, Ting-Wen Pai, Wen-Chieh Chen
  • Publication number: 20210225701
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20210208635
    Abstract: An electronic device includes a casing, a stylus, a first magnet, a magnetic ring, and a pair of second magnets. The casing has a surface and an accommodation groove recessed from the surface. The stylus has a front end and a rear end. The first magnet is disposed at one of the front end and the rear end of the stylus, and the magnetic ring is disposed at the other of the front end and the rear end of the stylus. The second magnets are disposed in the casing and located below the accommodation groove, where locations of the first magnet and the magnetic ring correspond to locations of the second magnets.
    Type: Application
    Filed: August 13, 2020
    Publication date: July 8, 2021
    Applicant: Acer Incorporated
    Inventors: Yu-Shih Wang, Wen-Chieh Tai, Cheng-Nan Ling, Chih-Chun Liu
  • Publication number: 20210202399
    Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.
    Type: Application
    Filed: July 31, 2020
    Publication date: July 1, 2021
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Kao-Feng LIN, Hsu-Kai CHANG, Shuen-Shin LIANG, Sung-Li WANG, Yi-Ying LIU, Po-Nan YEH, Yu Shih WANG, U-Ting CHIU, Chun-Neng LIN, Ming-Hsi YEH
  • Publication number: 20210202305
    Abstract: In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Po-Nan Yeh, Yu Shih Wang, Ming-Hsi Yeh
  • Publication number: 20210202238
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: June 22, 2020
    Publication date: July 1, 2021
    Inventors: Yu Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20210193517
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: 11009974
    Abstract: A touch pad structure includes a first casing, a second casing, a touch pad, an elastic element, a button, and an adjusting element. The first casing has an opening and is disposed on the second casing. The touch pad is disposed in the opening. The touch pad has a pivot portion and a movable portion. The pivot portion is pivoted to the first casing. A side of the movable portion facing the second casing is provided with a trigger. The elastic element is located between the first casing and the second casing. The elastic element has a first end and a second end. The button is aligned to the trigger and abuts against the first end of the elastic element. The adjusting element rotatably and movably penetrates through the second casing and is aligned to the button. The adjusting element abuts against the second end of the elastic element.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 18, 2021
    Assignee: Acer Incorporated
    Inventors: Ting-Wen Pai, Chih-Chun Liu, Yu-Shih Wang, Chien-Yuan Chen
  • Publication number: 20210134660
    Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
    Type: Application
    Filed: June 19, 2020
    Publication date: May 6, 2021
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Chia-Cheng Chen, Liang-Yin Chen, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20210134662
    Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Yu Shih Wang, Shian Wei Mao, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 10971396
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20210055762
    Abstract: An electronic device is provided, including a main body, a cover movably connected to the main body, a biasing element connected to the cover and the main body, a movable member movably disposed on the main body, and a magnetic element disposed on the movable member. When the cover is located in a closed position relative to the main body, the cover is attracted by the magnetic element and restricted in the closed position. When the movable member is pushed by an external force to move from its initial position to a first position, the movable member and the magnetic element separate from the cover, and the biasing element drives the cover to move from the closed position to an open position.
    Type: Application
    Filed: April 10, 2020
    Publication date: February 25, 2021
    Inventors: Ting-Wen PAI, Wen-Chieh TAI, Cheng-Nan LING, Chih-Chun LIU, Yu-Shih WANG
  • Publication number: 20210011565
    Abstract: A touch pad structure includes a first casing, a second casing, a touch pad, an elastic element, a button, and an adjusting element. The first casing has an opening and is disposed on the second casing. The touch pad is disposed in the opening. The touch pad has a pivot portion and a movable portion. The pivot portion is pivoted to the first casing. A side of the movable portion facing the second casing is provided with a trigger. The elastic element is located between the first casing and the second casing. The elastic element has a first end and a second end. The button is aligned to the trigger and abuts against the first end of the elastic element. The adjusting element rotatably and movably penetrates through the second casing and is aligned to the button. The adjusting element abuts against the second end of the elastic element.
    Type: Application
    Filed: February 11, 2020
    Publication date: January 14, 2021
    Applicant: Acer Incorporated
    Inventors: Ting-Wen Pai, Chih-Chun Liu, Yu-Shih Wang, Chien-Yuan Chen
  • Patent number: 10879656
    Abstract: A plug connector includes a conductive body, an insulative body, and a ring shape conductive terminal. The conductive body has an assembling hole. The insulative body is sleeved on the conductive body, wherein the insulative body has an opening hole and the assembling hole is aligned with the opening hole. The ring shape conductive terminal is assembled in the assembling hole, wherein the ring shape conductive terminal includes a conductive inner ring and the conductive inner ring includes a plurality of conductive portions. The conductive portions are arranged circularly and each conductive portion has at least two conductive contacts.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: December 29, 2020
    Assignee: Acer Incorporated
    Inventors: Yu-Shih Wang, Chih-Chun Liu, Wen-Chieh Tai
  • Publication number: 20200402859
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu