Patents by Inventor Yu Ting Lin

Yu Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220197132
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Publication number: 20220199514
    Abstract: The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Applicant: InnoLux Corporation
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Patent number: 11366604
    Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: June 21, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ko-Chin Chang, Ming-Jen Chang, Cheng-Hsiao Lai, Yu-Syuan Lin, Chi-Fa Lien, Ying-Ting Lin, Yung-Tsai Hsu
  • Publication number: 20220190237
    Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20220190160
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 16, 2022
    Inventors: Chi-Hsuan Tang, Chung-Ting Huang, Bo-Shiun Chen, Chun-Jen Chen, Yu-Shu Lin
  • Publication number: 20220189871
    Abstract: The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 16, 2022
    Inventors: KHADERBAD MRUNAL ABHIJITH, YU-YUN PENG, FU-TING YEN, CHEN-HAN WANG, TSU-HSIU PERNG, KENG-CHU LIN
  • Patent number: 11360524
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 14, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20220169281
    Abstract: A trajectory determination method for a vehicle is provided. A target vehicle trajectory is determined from among multiple candidate vehicle trajectories by considering, for each of the candidate vehicle trajectories, presence or absence of a front obstacle, presence or absence of a potentially-colliding obstacle, and a condition related to lane change, so as to enhance driving safety of the vehicle.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Applicant: Automotive Research & Testing Center
    Inventors: Yu-Ting LIN, Tsung-Ming HSU
  • Publication number: 20220170669
    Abstract: An apparatus combining a solar tracker and a dual heat source collector includes a heat engine assembly and the solar tracker. The heat engine assembly includes a heat collector, a heat collecting lens, and a heat engine. The heat collector includes a solar heat collecting room and a heat source room. The heat collecting lens is arranged on the heat collector and corresponds to the solar heat collecting room. The heat engine is located in the solar heat collecting room. The solar tracker includes a primary mirror, a secondary mirror, a pivot member, and a driving member. The primary mirror has a first reflective surface and a back surface. The primary mirror has a mounting hole passing through the primary mirror. The secondary mirror is mounted above the primary mirror.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: CHING-HSIANG CHENG, TSUNG-CHIEH CHENG, YEN-FEI CHEN, YU-TING LIN, SHANG-TING HUANG
  • Publication number: 20220171439
    Abstract: A portable electronic device including a first body, a second body, a hinge mechanism, a driving mechanism and a door is provided. The first body has a bottom and a heat dissipating opening located at the bottom. The second body is connected to the first body through the hinge mechanism. The driving mechanism is connected to the hinge mechanism. The door is disposed corresponding to the heat dissipating opening and is pivoted to the bottom of the first body. The door is connected to the driving mechanism and closes the heat dissipating opening in a mode. In another mode, the driving mechanism drives the door to rotate with respect to the first body, open the heat dissipating opening, and lift the first body.
    Type: Application
    Filed: September 29, 2021
    Publication date: June 2, 2022
    Applicant: Acer Incorporated
    Inventors: Yu-Wen Lin, Huei-Ting Chuang, Yen-Chieh Chiu, Po-Yi Lee, Hung-Chi Chen, Chao-Di Shen
  • Publication number: 20220172945
    Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.
    Type: Application
    Filed: February 14, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Shih Wang, Hong-Jie Yang, Chia-Ying Lee, Po-Nan Yeh, U-Ting Chiu, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20220173000
    Abstract: The embodiments of the disclosure provide a manufacturing method of a package circuit, including the following steps. A circuit structure including a plurality of conductive pads is formed. A liquid crystal layer is formed on the circuit structure. An inspection step is performed, and the inspection step includes determining the conductivity of the conductive pads according to the result of the rotation of a liquid crystal layer oriented with an electric field. In addition, the liquid crystal layer is removed.
    Type: Application
    Filed: November 4, 2021
    Publication date: June 2, 2022
    Applicant: Innolux Corporation
    Inventors: Yeong-E Chen, Bi-Ly Lin, Kuang Chiang Huang, Yu Ting Liu
  • Publication number: 20220165689
    Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.
    Type: Application
    Filed: February 13, 2022
    Publication date: May 26, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
  • Publication number: 20220165628
    Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.
    Type: Application
    Filed: May 10, 2021
    Publication date: May 26, 2022
    Inventors: Yeong-E CHEN, Kuang-Chiang HUANG, Yu-Ting LIU, Yi-Hung LIN, Cheng-En CHENG
  • Patent number: 11340525
    Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po Hsuan Li, Yu-Ting Lin, Yun-Yue Lin, Huai-Tei Yang
  • Patent number: 11342321
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.
    Type: Grant
    Filed: January 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Publication number: 20220155555
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion for holding an optical element, a fixed portion, a driving assembly used for driving the movable portion to move relative to the fixed portion, and an adhesive element. The movable portion is movable relative to the fixed portion, and the fixed portion includes a case and a bottom affixed on the case. The case has a top wall and a side wall. The top wall is plate-shaped and is perpendicular to a main axis, and the side wall is not parallel to the top wall. An accommodating space for accommodating the movable portion is formed between the case and the bottom. The adhesive element is in direct contact with the bottom, the case, and the driving assembly.
    Type: Application
    Filed: February 7, 2022
    Publication date: May 19, 2022
    Inventors: Kun-Shih LIN, Yu-Sheng LI, Shih-Ting HUANG, Yi-Hsin NIEH, Yu-Huai LIAO
  • Publication number: 20220158232
    Abstract: An electrolyte and a fabricating method thereof, and a lithium battery are described. The fabricating method of the electrolyte has steps of: adding a PVDF-based polymer and a PMA-based polymer to a liquid electrolyte to form a mixture, wherein the liquid electrolyte comprises a lithium salt; heating the mixture to between 60 and 100° C. for more than 4 hours, so as to form a transparent solution; and cooling the transparent solution to form the electrolyte. The electrolyte is a gel-state electrolyte between ?60 and 80° C., which is suitable for use as an electrolyte in a lithium battery.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 19, 2022
    Inventors: Yu-hsing LIN, Hsisheng TENG, Yi-han SU, Subramani RAMESH, Thi Tuyet Hanh NGUYEN, Yu-ting HUANG
  • Publication number: 20220139707
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20220122992
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate comprising an array area and a peripheral area adjacent to the array area; word line structures positioned in the array area; a word line hard mask layer positioned on the array area; a word line protection layer positioned on the word line hard mask layer; a gate electrode layer positioned on the peripheral area and separated from the word line hard mask layer and the word line protection layer; a peripheral protection layer positioned on the to gate electrode layer; and a first hard mask layer positioned over the array area and the peripheral area. A horizontal distance between the word line protection layer and the gate electrode layer is greater than or equal to three times of a thickness of the first hard mask layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Inventors: HUI-LIN CHEN, MAO-YING WANG, YU-TING LIN, LAI-CHENG TIEN