Patents by Inventor Yu Ting Lin

Yu Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10923481
    Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: February 16, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
  • Patent number: 10899050
    Abstract: The present subject matter relates to fabrication of micro-arc oxidation (MAO) based insert-molded components. In an example implementation, a method of fabricating a MAO based insert-molded component comprises forming an insert-molded component and oxidizing the insert-molded component through MAO. The insert-molded component has a metal body molded with a plastic body. On oxidation of the insert-molded component through MAO an oxide layer is formed on the metal body.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 26, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chi Hao Chang, Kuan-Ting Wu, Yu-Ling Lin
  • Patent number: 10896500
    Abstract: An image information display method, an image information display system and a display. The method includes: capturing a background image of the display; obtaining an object according the background image; capturing a relative movement information between a first user and the object; capturing a visual information corresponding to the first user; determining whether a reading comfort degree corresponding to the object meets a predetermined condition according to the relative movement information and the visual information; displaying a dynamic information corresponding to the object by the display when the reading comfort degree meets the predetermined condition; and not displaying the dynamic information corresponding to the object by the display when the reading comfort degree does not meet the predetermined condition.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 19, 2021
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shin-Hong Kuo, Kuan-Ting Chen, Yu-Hsin Lin, Yi-Shou Tsai, Yu-Hsiang Tsai, Yi-Hsiang Huang
  • Publication number: 20210013075
    Abstract: This invention proposes a substrate carrier and an air diffusion module thereof. The air diffusion module comprises a cover, at least one air inlet, an airtight layer, an air diffusion layer and an engaging portion. The at least one air inlet is connected with the cover, and the airtight layer is connected with the cover and the at least one air inlet. Furthermore, the air diffusion layer is connected with the cover via the airtight layer, and the engaging portion engages and tightly connected with the cover, the at least one air inlet and the air diffusion layer. The engaging portion is configured on the substrate carrier as a semiconductor container.
    Type: Application
    Filed: October 6, 2019
    Publication date: January 14, 2021
    Inventors: MING-CHIEN CHIU, CHIH-MING LIN, PO-TING LEE, YU-CHEN CHU
  • Publication number: 20210013033
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
  • Publication number: 20210012839
    Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
    Type: Application
    Filed: May 13, 2020
    Publication date: January 14, 2021
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
  • Patent number: 10891917
    Abstract: A transparent display system including a display panel, a data acquisition module and a computation module is provided. The data acquisition is adapted to capture a field luminance of a field where the display panel is located and a display information luminance of display information of the display panel. The computation module determines whether a luminance contrast of the display information falls within a range from a lower boundary to an upper boundary, wherein the luminance contrast of the display information equals to the field luminance plus the display information luminance and then divided by the field luminance. If it is determined that the luminance contrast of the display information does not fall within the range from the lower boundary to the upper boundary, a luminance contrast optimization procedure is performed. An operation method of the transparent display system is also provided.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 12, 2021
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Shin-Hong Kuo, Cheng-Chung Lee, Kuan-Ting Chen, Yi-Shou Tsai, Yu-Hsin Lin
  • Patent number: 10881902
    Abstract: An arm muscular strength training and rehabilitation apparatus has a body, an angle meter, a handle, a force sensing device and a main control unit. The body has a housing and a variable resistance device. The variable resistance device is disposed in the housing. The angle meter is disposed on the variable resistance device. The handle is disposed pivotally on the variable resistance device and has a suspension arm and a handlebar bracket. The force sensing device is disposed on handlebar bracket of the handle. The main control unit connects electrically to the variable resistance device, the angle meter and the force sensing device to receive the angle signal and the force sensing signal and controls resistance of the variable resistance device according to the angle signal and the force sensing signal. The apparatus disposing the force sensing device on the handle prevents measuring time lag and increase measuring precision.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 5, 2021
    Assignee: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY
    Inventors: Yao-Jung Shiao, Tun-Hao Yang, Guan-Ting Chen, Ming-Cheng Hsih, Cheng-Hsien Huang, Yu-Ju Lin
  • Publication number: 20200411672
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: September 6, 2020
    Publication date: December 31, 2020
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Patent number: 10879140
    Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yen Lin, Yu-Chih Liu, Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho
  • Patent number: 10879215
    Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li-Hao Lyu, Chieh-Ju Tsai, Yu-Kai Lin, Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng, Yu-Ting Lu
  • Patent number: 10879111
    Abstract: A method according to some embodiments of the present disclosure includes providing a workpiece that include an opening and a top surface, depositing a dielectric material over the workpiece and into the opening to form a first dielectric layer that has a top portion over the top surface and a plug portion in the opening, treating the first dielectric layer to convert top portion into a second dielectric layer different from the first dielectric layer, and selectively removing the second dielectric layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Yen, Ting-Ting Chen, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20200400612
    Abstract: A method of measuring hematocrit is provided. The method for measuring hematocrit includes the following steps. A test strip is provided. The test strip includes a reaction region and a pair of electrodes disposed in the reaction region. A whole blood sample is entered to the reaction region. After the whole blood sample enters the reaction region, a plurality of sets of square wave voltages are intermittently applied to the pair of electrodes based on a square wave voltammetry method to obtain a plurality of feedbacks related to hematocrit. An interval between two adjacent sets of square wave voltages ranges from 0.1 seconds to 4 seconds. A feedback of an n-th set of square wave voltages is obtained to calculate a hematocrit value of the whole blood sample and n is a positive integer greater than 1. A hematocrit value is calculated according to the feedback.
    Type: Application
    Filed: September 7, 2020
    Publication date: December 24, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chu-Hsuan Chen, Yu-Fang Yen, Yi-Ting Tung, Fen-Fei Lin, Yi-Yun Yuan, Wen-Pin Hsieh
  • Publication number: 20200395286
    Abstract: The present disclosure provides an electronic device including a substrate, a first pad, a second pad and an integrated circuit chip. The first pad is disposed on the substrate. The second pad is disposed on the first pad and electrically connected to the first pad. The integrated circuit chip is disposed on the second pad and is electrically connected to the second pad. The second pad has a plurality of curved corners.
    Type: Application
    Filed: May 11, 2020
    Publication date: December 17, 2020
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Patent number: 10868112
    Abstract: A circuit device includes core circuitry. The circuit device further includes a guard ring surrounding the core circuitry. The guard ring includes a first plurality of fin structures arranged in a first direction parallel to a first side of the core circuitry, wherein adjacent fin structures of the first plurality of fin structures are separated by a first distance. The guard ring further includes a second plurality of fin structures arranged in a second direction parallel to a second side of the core circuitry, wherein adjacent fin structures of the second plurality of fin structures are separated by a second distance, and the second distance is smaller than the first distance.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yen Lin, Wun-Jie Lin, Yu-Ti Su, Bo-Ting Chen, Jen-Chou Tseng, Kuo-Ji Chen, Sun-Jay Chang, Min-Chang Liang
  • Patent number: 10867845
    Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Ching-Hwanq Su, Liang-Yueh Ou Yang, Ming-Hsing Tsai, Yu-Ting Lin
  • Patent number: 10868239
    Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
  • Publication number: 20200387200
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Application
    Filed: January 21, 2020
    Publication date: December 10, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20200387476
    Abstract: A cloud-based migration system exposes a source-independent application programming interface for receiving data to be migrated. The data is uploaded and stored as a single entity in a cloud-based storage system. A migration system then accesses the migration package and begins migrating the data to its destination, from the cloud-based storage system.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: Joe Keng YAP, Mahadevan Thangaraju, Sean L. Livingston, Roberta Cannerozzi, Ghania Moussa, Ron Shimon Estrin, Yu-Ting Lin, Simon Bourdages, Trung Duc Nguyen, Wenyu Cai, Zachary Adam Koehne, Patrick J. Simek, Sukhvinder Singh Gulati, Ben Canning
  • Patent number: 10862023
    Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu