Abstract: A device for treating a user's skin using plasma is provided. The device comprises a plasma generation assembly and a power supply. The plasma generation assembly comprises a discharge electrode including a first surface; a first dielectric material layer provided on the first surface of the discharge electrode and the first surface, a ground electrode surrounding the discharge electrode, and an insulation member spacing around the discharge electrode from the ground electrode. The power supply configured to apply power to the plasma generation assembly so that plasma is generated from the first surface of the discharge electrode to the ground electrode and between the first dielectric material layer and the user's skin.

Abstract: A method for assessing occurrence of heart failure includes the following steps. A heart failure assessment program established is provided. A target ECG signal data of the subject is provided, wherein the target ECG signal data includes a plurality of target heartbeat waveform data and a plurality of target heart rate data. A data pre-processing step is performed, wherein the target ECG signal data is pre-processed by the data processing module so as to obtain a processed target ECG signal data. An analyzing step is performed, wherein the processed target ECG signal data is analyzed by the heart failure assessment program so as to obtain a heart failure occurrence assessing result, and the heart failure occurrence assessing result presents a heart failure occurring condition and the severity of the heart failure of the subject.

Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of capacitors, and a first supporting layer. The plurality of capacitors are disposed on the substrate. Each of the capacitors extends along a first direction. Each of the plurality of capacitors includes a first capacitor electrode, a second capacitor electrode, and a capacitor dielectric separating the first capacitor electrode from the second capacitor electrode. The first supporting layer is disposed on the substrate. The first supporting layer extends along a second direction different from the first direction. The capacitor dielectric includes a first surface and a second surface which are disposed on two opposite sides along the first direction. The second surface is exposed by the first capacitor electrode. The first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.

Abstract: A method of manufacturing a semiconductor structure includes: forming a first oxide layer over a landing pad layer; forming a middle patterned dielectric layer over the first oxide layer; sequentially forming a second oxide layer and a top dielectric layer over the middle patterned dielectric layer; forming a trench through the top dielectric layer, the second oxide layer and the first oxide layer; conformally forming a bottom conductive layer in the trench; removing a portion of the top dielectric layer adjacent to the trench to expose a portion of the second oxide layer beneath the portion of the top dielectric layer; and performing an etching process to remove the second oxide layer and the first oxide layer. A semiconductor structure is also provided.

Abstract: A system includes one or more data processors and a non-transitory computer-readable storage medium containing instructions which, when executed on the one or more data processors, cause the one or more data processors to perform operations. The operations include receiving a modified basic input-output system (BIOS) setting using an application programming interface (API). The modified BIOS setting includes an attribute describing at least one extensible firmware interface (EFI) variable. The operations further include storing the modified BIOS setting in a future setting data structure in a baseboard management controller (BMC). The operations further include providing a current setting data structure stored in the BMC. The operations further include replacing at least a portion of the current setting data structure with the modified BIOS setting to provide a modified current setting data structure. The modified current setting data structure is then applied to the system.

Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is located in the third dielectric layer and extends across the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and a portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.

Abstract: A dynamic random access memory includes an array region, a bottom capacitor array located in the array region, and a top capacitor array located in the array region and located on the bottom capacitor array. The bottom capacitor array is single-sided capacitor array. The top capacitor is a double-sided capacitor array.

Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.

Abstract: The present invention relates to a biosensor device for sensing an analyte over a period of time using particle motion, the biosensor device having a surface and a particle, wherein the particle and/or the surface are functionalized, and wherein the biosensor device has a first state in which the particle is associated with the surface and a second state in which the particle is not associated with the surface, and wherein switching between the first and second states depends on the presence, absence and/or concentration of the analyte, whereby motion characteristics of the particle change depending on the presence, absence and/or concentration of the analyte, thereby allowing sensing of the analyte by measuring changes in a spatial coordinate parameter of the particle relative to the surface, and wherein the properties of the particle and surface are selected such that in the second state the particle is within the vicinity of the surface such that the biosensor is able to measure changes in a spatial coordi

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a sacrificial structure disposed on a substrate; arranging a photomask to cover the sacrificial structure, wherein the photomask includes a plurality of transparent portions, a plurality of central opaque portions, at least one first edge opaque portion and at least one second edge opaque portion between the first edge opaque portion and the central opaque portions; removing portions of the sacrificial structure to form a plurality of central openings, at least one first edge opening and at least one second edge opening through the central opaque portions, the first edge opaque portion, the second edge opaque portion and the transparent portions; and forming at least one edge word line on the substrate through the second edge opening and forming a plurality of central word lines on the substrate through the central openings.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.