Patents by Inventor Yu Wang

Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119338
    Abstract: An operation and maintenance method and system for automatically and uniformly managing nodes of bastion host can be abstracted as follows: master control dispatches a Master of a certain area node to issue and execute a certain task, and unified management is naturally achieved; the design concept can be continued subsequently. A Master host in the node serves as a master controller of the node, and related contents including a tool script library, a crontab task and a configuration file are preset in a Redis of the node in advance; when a new machine is accessed to a certain node, the new machine performs Salt-Master access management of the node where the new machine is located, and the corresponding machine is controlled to complete the corresponding task through a takeover program; therefore, unified and automatic management is realized.
    Type: Application
    Filed: September 5, 2023
    Publication date: April 10, 2025
    Applicant: Hangzhou PingPong Intelligence Technology Co., Ltd.
    Inventors: Xiaohui JIA, Peng CHEN, Zhehui ZHAO, Yu CHEN, Ning WANG, Shuai LU
  • Publication number: 20250120184
    Abstract: A semiconductor structure includes first standard cells having first active regions formed over first alternating n-type and p-type wells, the first active regions and the first alternating n-type and p-type wells each extends lengthwise along a first direction, each of the first standard cells includes a first n-type well and a first p-type well; and second standard cells adjacent to the first standard cells, the second standard cells having second active regions formed over second alternating n-type and p-type wells, the second active regions and the second alternating n-type and p-type wells each extends lengthwise along the first direction, each of the second standard cells includes a second n-type well and a second p-type well. The first standard cells have a first cell height, the second standard cells have a second cell height, and the second cell height is greater than the first cell height.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: Yu-Lung Tung, Xiaodong Wang, Jhon Jhy Liaw
  • Publication number: 20250117602
    Abstract: A large model-based recommendation method includes: determining description information of interested content corresponding to a target user; inputting a content to be recommended, the description information of interested content and current popular search sentences into a large model to generate at least one recommendation card corresponding to the content to be recommended, in which the recommendation card contains a recommendation word associated with the content to be recommended; obtaining a current behavior characteristic of the target user; and in response to the current behavior characteristic satisfying a display condition of the recommendation card, displaying the recommendation card corresponding to at least one content to be recommended.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Applicant: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventors: Zhaoxu Wang, Qiang Xie, Yuhang Zheng, Shouke Qin, Zonggang Wu, Yuanhua Shao, Yan Wang, Ruohan Chang, Qingqing Wu, Lu Wang, Songge Guo, Chang Li, Xi Cao, Qian Wu, Xiaoyu Hu, Huijie Liu, Yu Guo, Hui Xue, Rufeng Cheng
  • Publication number: 20250120166
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
  • Publication number: 20250120271
    Abstract: Disclosed is a display panel, which comprises: a base substrate, and, disposed on the base substrate, a circuit structure layer and a light-emitting structure layer. The base substrate comprises a first display area, and a second display area located on at least one side of the first display area. The circuit structure layer comprises a plurality of first pixel circuits and a plurality of second pixel circuits which are located in the second display area, and a plurality of connecting lines extending from the second display area to the first display area. The light-emitting structure layer comprises a plurality of first light-emitting elements located in the first display area, and a plurality of second light-emitting elements located in the second display area. At least one first pixel circuit is electrically connected to at least one first light-emitting element by means of at least one connection line.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Inventors: Yuxuan PAN, Yu TIAN, Pei WANG, Kai ZHANG
  • Publication number: 20250114450
    Abstract: The present invention relates to the field of tumor treatment and immunology biology. Provided are a pharmaceutical combination containing an anti-PD-1-anti-VEGFA bispecific antibody, and the use thereof. Specifically, the pharmaceutical combination comprises at least one bispecific antibody and at least one PARP inhibitor, wherein the bispecific antibody comprises a first protein functional region for targeting PD-1 and a second protein functional region for targeting VEGFA; and according to the EU numbering system, the heavy chain constant region of an immunoglobulin contained in the bispecific antibody is mutated at two sites, i.e. site 234 and site 235, and after mutation, the affinity constant of the bispecific antibody to Fc?RI, Fc?RIIa, Fc?RIIIa and/or C1q is reduced compared with the affinity constant of the bispecific antibody thereto before mutation.
    Type: Application
    Filed: March 10, 2022
    Publication date: April 10, 2025
    Inventors: Zhongmin WANG, Baiyong LI, Yu XIA
  • Publication number: 20250118638
    Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Jian Yin, Lin Chen, Ziwei Yu, Xiaobin Wang, Zhiqiang Niu, Kuan-Hung Li
  • Publication number: 20250116031
    Abstract: One embodiment of the present disclosure provides a scintillation crystal and a method and a device for preparing the scintillation crystal. A molecular formula of the scintillation crystal is: Cey:Cas:Lu2(1-xysz)Y2zSc2xSiO5, wherein x=0-1, y=0.0000001-0.06, z=0.00001-0.5, s=0.0000001-0.05.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 10, 2025
    Applicant: MEISHAN BOYA ADVANCED MATERIALS CO., LTD.
    Inventors: Yu WANG, Weiming GUAN
  • Publication number: 20250118913
    Abstract: A bus connection wire forward soldering structure includes a circuit board, a flat cable and a fixing member, and the circuit board has a solder area, a docking area, first and second surfaces and an outgoing line direction. The solder area is disposed on the first surface, the flat cable includes a solder terminal, first and second attaching sections, a folding section and a main body section, the solder terminal faces the docking area and is electrically connected to the solder area, the folding section is connected between the first and second attaching sections, the main body section extends along the outgoing line direction, the fixing member covers the solder terminal, the folding section, the first and second attaching sections, the fixing member has a notch defined corresponding to the second surface and located at junction of the second attaching section and the main body section junction.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yu WANG, Chieh-Ming CHENG
  • Publication number: 20250118367
    Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
    Type: Application
    Filed: November 6, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Yu-Der Chih, Yih Wang
  • Publication number: 20250115939
    Abstract: The present disclosure relates to a neural repair protein composition. The preparation thereof includes the following steps: adding 20 U/mL-35 U/mL of any one of or a combination of nuclease or omnipotent nuclease to a cell protein extract, performing enzymatic hydrolysis at 37° C.±1° C. for 15-40 minutes, and separating and purifying the prepared enzymatic hydrolysate. The neural repair protein composition of the present disclosure has the effects of cell repair and nerve damage repair, and can be used to repair nerve damage caused by diseases such as central nervous system damage, neurodegenerative diseases, stroke, brain damage, ataxia, cerebral hemorrhage, Alzheimer's disease, Parkinson's disease, senile dementia or complications thereof. It has the advantages of good stability, high bioavailability, safety and effectiveness, and is easy to produce and store.
    Type: Application
    Filed: January 28, 2023
    Publication date: April 10, 2025
    Inventors: Yu WANG, Wenyong GAO, Lin CHEN, Jianjun LI
  • Publication number: 20250116891
    Abstract: A liquid crystal display includes a display panel and a driving unit. The display panel includes a plurality of resetting sections, which correspond to display a plurality of screens, respectively. There is a first voltage difference between a corresponding one of the column voltages and a corresponding one of the row voltages of one of the resetting sections, and there is a second voltage difference between a corresponding one of the column voltages and a corresponding one of the row voltages of another of the resetting sections. The second voltage difference reaching a second maximum voltage difference value is after the first voltage difference reaching a first maximum voltage difference value by a delay time, so as to clear the screens.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 10, 2025
    Inventors: Ting Yu TAI, Sheng Yao WANG, Wu Chang YANG, Chi Chang LIAO
  • Publication number: 20250118912
    Abstract: A bus connection cable reverse-welding structure includes a circuit board, a flat cable, and a first line. The circuit board includes a wiring side, an insertion side, a welding area, a first mating area. A wire exit direction is defined from the wiring side toward the insertion side. The welding area is on the wiring side, and the first mating area is on the insertion side. The flat cable includes a main segment, an attached segment, and a welding end. The main segment extends along the wire exit direction, and the attached segment is attached on the circuit board. The welding end is electrically connected to the welding area. The first line is arranged in the circuit board and includes a first embedded segment and a first extension segment. The first embedded segment is embedded in the circuit board and connected to the welding area.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yu WANG, Chieh-Ming CHENG
  • Publication number: 20250118682
    Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
  • Publication number: 20250118678
    Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Jhih-Yu Wang, Yu-Hsiang Hu
  • Publication number: 20250119442
    Abstract: A modular adversarial training data generator (“generator”) generates adversarial training data for a machine learning (ML) model to detect malicious protocol data units (PDUs). The adversarial training data mimics high volume cyberattacks by perturbing PDUs to bypass malicious detection systems. For HyperText Transfer Protocol (HTTP) PDUs, the generator rearranged, replaces, and grid searches values of HTTP header fields to generate the adversarial training data. The generator further biases grid search based on metrics for values of HTTP header fields that quantify impact of replacing the values on malicious verdicts by ML models trained on the adversarial training data.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Ajaya Neupane, Yu Fu, Lei Xu, Mei Wang, Fikirte Ayalke Demmese
  • Publication number: 20250120122
    Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Chen-Ming Lee, Shih-Chieh Wu, Po-Yu Huang, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12272363
    Abstract: A method includes receiving training data that includes unspoken text utterances, un-transcribed non-synthetic speech utterances, and transcribed non-synthetic speech utterances. Each unspoken text utterance is not paired with any corresponding spoken utterance of non-synthetic speech. Each un-transcribed non-synthetic speech utterance is not paired with a corresponding transcription. Each transcribed non-synthetic speech utterance is paired with a corresponding transcription. The method also includes generating a corresponding synthetic speech representation for each unspoken textual utterance of the received training data using a text-to-speech model. The method also includes pre-training an audio encoder on the synthetic speech representations generated for the unspoken textual utterances, the un-transcribed non-synthetic speech utterances, and the transcribed non-synthetic speech utterances to teach the audio encoder to jointly learn shared speech and text representations.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 8, 2025
    Assignee: Google LLC
    Inventors: Andrew Rosenberg, Zhehuai Chen, Bhuvana Ramabhadran, Pedro J. Moreno Mengibar, Yuan Wang, Yu Zhang
  • Patent number: 12274180
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 12270024
    Abstract: The present invention relates to the technical field of microorganisms, and specifically to engineered microorganisms expressing acetoacetyl-CoA reductase variants and methods for increasing the proportion of 3-hydroxyhexanoic acid in PHA. The acetoacetyl-CoA reductase variants and their coding genes provided by the present invention can significantly increase the proportion of 3-hydroxyhexanoic acid in PHA produced by strains; the proportion of 3-hydroxyhexanoic acid in PHA produced by the engineered Ralstonia eutropha constructed utilizing the acetoacetyl-CoA reductase variants and their coding genes provided by the present invention is significantly increased, which provides new genes and strain resources for strains producing poly(3-hydroxybutyrate-co-3-10 the development of engineered hydroxyhexanoate) with high proportion of 3-hydroxyhexanoic acid.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: April 8, 2025
    Assignee: SHENZHEN BLUEPHA BIOSCIENCES CO., LTD.
    Inventors: Jin Yin, Yu Wang, Jiajia Li, Jie Hou, Liang Zou, Zixian Chen