Patents by Inventor Yu Wang

Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250160158
    Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate; a pixel circuit layer, on the base substrate; an anode layer, at a side of the pixel circuit layer away from the base substrate, the pixel circuit layer includes a plurality of pixel driving circuits, the plurality of pixel driving circuits include a first pixel driving circuit, the anode layer includes a plurality of anodes, the plurality of anodes include a first anode, the first anode includes a first main body portion and a first connection portion, and the first connection portion is electrically connected to the first pixel driving circuit, an orthographic projection of the first anode on the base substrate covers one thin film transistor in the first pixel driving circuit.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lulu YANG, Tinghua SHANG, Guomeng ZHANG, Yu WANG, Xiaofeng JIANG, Xin ZHANG, Yupeng HE, Yi QU, Biao LIU, Mengmeng DU, Xiangdan DONG, Hongwei MA
  • Patent number: 12300739
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12301992
    Abstract: This application provides an image blur degree determining method and a related device thereof, and relates to the field of image processing. The image blur degree determining method includes: obtaining an original image; determining a homography transformation matrix corresponding to each image block arranged in a column direction in the original image, where the column direction is perpendicular to a row direction in which an electronic device performs row-by-row exposure; and determining a blur degree of the original image based on each image block and the corresponding homography transformation matrix. This application can implement an objective of quickly calculating a blur degree of an image without being affected by image content.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: May 13, 2025
    Assignee: Honor Device Co., Ltd.
    Inventors: Tiantian Zhang, Yu Wang, Zhiqi Li, Ning Wang, Congchao Zhu
  • Patent number: 12299579
    Abstract: This document relates to training of machine learning models. One example method involves providing a machine learning model having one or more mapping layers. The one or more mapping layers can include at least a first mapping layer configured to map components of pretraining examples into first representations in a space. The example method also includes performing a pretraining stage on the one or more mapping layers using the pretraining examples. The pretraining stage can include adding noise to the first representations of the components of the pretraining examples to obtain noise-adjusted first representations. The pretraining stage can also include performing a self-supervised learning process to pretrain the one or more mapping layers using at least the first representations of the training data items and the noise-adjusted first representations of the training data items.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: May 13, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Xiaodong Liu, Hao Cheng, Yu Wang, Jianfeng Gao, Weizhu Chen, Pengcheng He, Hoifung Poon
  • Patent number: 12300306
    Abstract: A memory includes a peripheral circuit and a memory array. The memory array includes word lines. The peripheral circuit includes a driver, a repeater, and a discharge circuit. An output terminal of the driver is coupled with a controlled terminal of the repeater. An output terminal of the repeater is coupled with a controlled terminal of the discharge circuit. The discharge circuit is coupled with a word line in the memory array. The driver is configured to output a first control signal to the repeater. The repeater is configured to output a second control signal to the discharge circuit according to the first control signal.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: May 13, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Danyang Li, Daesik Song, Yu Wang, Zhichao Du
  • Patent number: 12301082
    Abstract: A stator includes a stator core and a stator winding. An inner wall of the stator core is provided with M winding slots, the M winding slots are uniformly disposed in a circumferential direction of the inner wall of the stator core. The stator winding includes flat wire conductors inserted in the winding slots, N layers of flat wire conductors are disposed in any one of the winding slots, and phase units of a first-phase winding, phase units of a second-phase winding, and phase units of a third-phase winding are sequentially and periodically arranged along the inner wall of the stator core. Each phase winding includes P parallel branches. Any one of the parallel branches connects flat wire conductors of M·N/3P layers.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: May 13, 2025
    Assignee: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Qiqi Guo, Yu Wang, Zhao Zhou, Yang Zheng
  • Patent number: 12300677
    Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: May 13, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
  • Patent number: 12300720
    Abstract: A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Wei Ju Lee
  • Patent number: 12300728
    Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.
    Type: Grant
    Filed: February 19, 2024
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi Yeong, Pei-Yu Wang, Chi On Chui
  • Patent number: 12299227
    Abstract: A display panel includes: a base substrate; a first touch layer including a first touch line; a touch insulation layer provided with a via hole at least partially located in the non-display region; and a second touch layer including a second touch line with different resistance per unit length from the first touch line and at least partially located in the non-display region. Orthographic projections of the second touch line and the first touch line on the base substrate at least partially overlap with each other, the second touch line is connected to the first touch line through the via hole; a part of the first touch line and/or the second touch line connected to the functional structure of the display panel forms a connection part, and the via hole is at least located on a side of the connection part away from the functional structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 13, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yuanqi Zhang, Yu Wang, Yi Zhang, Shun Zhang, Chang Luo
  • Publication number: 20250151561
    Abstract: A display substrate, a manufacturing method thereof, and a display device. In the display substrate, the sub-pixel driving circuit includes a driving transistor and a first reset transistor, and a gate electrode of the first reset transistor is electrically connected to the reset signal line pattern, a first electrode of the first reset transistor is electrically connected to the initialization signal line pattern, and a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor; and the shielding pattern is electrically connected to the power signal line pattern, an orthographic projection of the shielding pattern on the substrate overlaps an orthographic projection of the first electrode of the first reset transistor on the substrate.
    Type: Application
    Filed: January 14, 2025
    Publication date: May 8, 2025
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tinghua SHANG, Yi ZHANG, Tingliang LIU, Linhong HAN, Huijuan YANG, Shun ZHANG, Yu WANG
  • Publication number: 20250151326
    Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.
    Type: Application
    Filed: April 25, 2024
    Publication date: May 8, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Pei-Yu WANG, Hsien-Chih HUANG, Chia-Hao YU
  • Publication number: 20250148945
    Abstract: A display panel is provided. The display panel includes display elements in a display area; a touch electrode layer at least partially in the display area, wherein the display elements and the touch electrode layer are absent in a window region that is at least partially surrounded by the display area; and a crack detection circuit. The crack detection circuit includes an integrated circuit; and a first conduction loop electrically connected to the integrated circuit. The first conduction loop includes a window region crack detection line substantially surrounding the window region; and at least a portion of the first conduction loop includes a first metal line in a first layer and a second metal line in a second layer, the first metal line connected to the second metal line through a via extending through a touch insulating layer.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 8, 2025
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Shun Zhang, Yuanqi Zhang, Ping Wen, Fan He, Yi Zhang, Yu Wang, Yang Zeng
  • Publication number: 20250151532
    Abstract: A display panel includes a drive backplane; a first electrode layer, including a plurality of first electrodes distributed in an array, where the first electrode includes a flat middle part and an edge part surrounding the middle part; a light-emitting function layer, at least partially covering the middle part; and a second electrode, covering the light-emitting function layer, and including a separating part and a plurality of flat parts separated by the separating part, where orthographic projections of the flat parts on the drive backplane are located in one-to-one correspondence within orthographic projections of the first electrodes on the drive backplane, the separating part includes a protruding area and a first recessed area connecting the protruding area and the flat part, and the protruding area is provided with a second recessed area recessed toward the drive backplane.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: Yu WANG, Kuanta HUANG, Qing WANG, Yongfa DONG, Chao YANG, Shipeng LI, Hui TONG, Shangquan SHI, Xiong YUAN, Dongsheng LI, Xiaobin SHEN
  • Publication number: 20250151433
    Abstract: A pixel array that includes some pixels with high absorption (HA) structures and other pixels without HA structures exhibits increased dynamic range for near infrared (NIR) light. Additionally, the pixel array is a uniform array of photodiodes and thus does not exhibit current leakage that would have been caused by irregular isolation structures. Additionally, the pixel array may further a lateral overflow integration capacitor to further increase the dynamic range for NIR light.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Cheng-Ying HO, Kai-Chun HSU, Wen-De WANG, Yuh HUANG, Cheng-Yu HSIEH, Hung-Yu WANG, Jen-Cheng LIU
  • Publication number: 20250151124
    Abstract: This application provides a random access method, an apparatus, and a system, which are applied to the field of communication technologies. The random access method provided in this application includes: First, a terminal device obtains first configuration information, where the first configuration information indicates a maximum quantity of repeated sending times of a preamble, and the maximum quantity of repeated sending times of the preamble is greater than 200. Then, the terminal device sends one or more preambles to a network device based on the first configuration information. According to the method, a current maximum quantity of repeated sending times of the preamble is extended, so that a decoding threshold for decoding the preamble by the network device is reduced, and a low uplink budget requirement of some scenarios can be met.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Chuili KONG, Ying CHEN, Xiaolu WANG, Yu WANG, Yinggang DU
  • Publication number: 20250144269
    Abstract: The present disclosure relates to a protein composition having a joint repair function. Preparation of the protein composition comprises the following steps: adding any one of or a combination of a nuclease or Benzonase nuclease of 20 U/mL-35 U/mL into a cell protein extract, placing same at 37° C.±1° C. for enzymatic hydrolysis for 15-40 minutes, and separating and purifying the prepared enzymatic hydrolysate to obtain the protein composition. The protein composition obtained in the present disclosure has the effects of cell repair, joint repair, or cartilage repair, and is used for preventing and treating any one of or a complication of traumatic arthropathy, degenerative osteoarthropathy, joint injury, refractory wound lesions, knee osteoarthrosis, or cartilage injury.
    Type: Application
    Filed: January 28, 2023
    Publication date: May 8, 2025
    Applicant: BEIJING DARWIN BIOTECH CO., LTD.
    Inventors: Yu WANG, Wenyong GAO, Lin CHEN, Jianjun LI
  • Publication number: 20250150550
    Abstract: A method for recording a video conference and a video conferencing system are provided. The method includes: providing a user interface to a display device, in which the user interface includes a first area, a second area, and a timeline; in response to obtaining an image corresponding to each of multiple participants from a video signal through a person recognition algorithm, displaying the image of each participant in the first area; in response to converting an audio segment of one of the participants obtained from an audio signal into text content through a voice processing algorithm, associating the text content with the corresponding one of the participants, and based on an order of speaking, displaying the text content in the second area; and adjusting a time length of the timeline according to a recording time of the video conference.
    Type: Application
    Filed: December 11, 2023
    Publication date: May 8, 2025
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Shuo-Yu Wang, Chan-An Wang, Hsiu-Ling Lin, Chung-Yi Huang
  • Publication number: 20250150555
    Abstract: A method for switching audio reception in a video conference and a video conferencing system are provided. In a case of starting the video conference, relative positions of participants in a conference space and behavioral events of participants are obtained by identifying a video signal. Based on the behavioral event of each participant, whether each participant is in a non-speaking behavior is determined. When a participant is determined to be a non-speaker in the non-speaking behavior, an audio reception range of an audio reception device is adjusted to filter a voice of the non-speaker based on the relative position of the non-speaker in the conference space. When a participant is determined to be a speaker not in the non-speaking behavior, the audio reception range of the audio reception device is adjusted to receive a voice of the speaker based on the relative position of the speaker in the conference space.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 8, 2025
    Applicant: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Shuo-Yu Wang, Chan-An Wang, Hsiu-Ling Lin, Chung-Yi Huang
  • Patent number: 12293053
    Abstract: A touch structure, a touch display panel, and a display device are provided. The touch structure includes a substrate and a first metal grid electrode layer, an insulating layer, a second metal grid electrode layer on the substrate. The first metal grid electrode layer is on a side of the second metal grid electrode layer away from the substrate; the first metal grid electrode layer includes a plurality of first metal grids formed by a plurality of first metal lines, the second metal grid electrode layer includes a plurality of second metal grids formed by a plurality of second metal lines, first portions of the plurality of the first metal lines and second portions of the plurality of the second metal lines have same line extension directions, respectively, and overlap with each other in a direction perpendicular to a surface of the substrate.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: May 6, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kemeng Tong, Cong Fan, Fan He, Yu Wang, Xiangdan Dong, Jiangtao Deng