Patents by Inventor Yu Wang

Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240129073
    Abstract: A first wireless device employs an uplink (UL) pre-transmission process to temporarily buffer data for processing prior to transmission of the resulting processed data to a second wireless device. To mitigate excessive delay of higher-priority data, higher-priority data is enqueued into the UL pre-transmission process without restriction (subject to capacity limitations), while lower-priority data is selectively enqueued into the UL pre-transmission process based on one or more criteria applied to a current volume of data in the input queue. Further, the first wireless device monitors the current transmission efficiency based on, for example, the current usage of transmission padding, and operates to dynamically adjust one or more of the criteria based on the monitored current transmission efficiency.
    Type: Application
    Filed: October 26, 2023
    Publication date: April 18, 2024
    Inventors: WeiChih Liao, Todd Ou, Yu Wang
  • Publication number: 20240128816
    Abstract: A variable flux permanent-magnet synchronous motor, a powertrain, and a fan are disclosed, which are applied to the field of motors. The variable flux permanent-magnet synchronous motor includes a stator system 10, a rotor system 20, and a variable magnet system 30. The variable magnet system 30 is located in the stator system 10 or the rotor system 20. The rotor system 20 includes a first permanent magnet 201. The variable magnet system 30 includes a second permanent magnet 301 and a heating apparatus 302. Coercive force of the second permanent magnet 301 is lower than coercive force of the first permanent magnet 201. The heating apparatus 302 is configured to heat the second permanent magnet 301, so that the second permanent magnet 301 has variable flux in a magnetic field.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Bin Lai, Yu Wang, Zijing Wang, Huanwen Huang
  • Publication number: 20240127993
    Abstract: Provided are an auxiliary alloy casting piece, a high-remanence and high-coercive force NdFeB permanent magnet, and preparation methods thereof. The method for preparing the auxiliary alloy casting piece includes the following steps: providing an auxiliary alloy material including, by mass percentage, 40% to 45% of Pr, 1% to 2% of Co, 0.5% to 1% of Ga, 0.6% to 0.8% of B, 0.1% to 0.2% of V, 0.3% to 0.7% of Ti, and a balance of Fe; smelting the auxiliary alloy material to obtain a smelted material; and subjecting the smelted material to a quick-setting casting to obtain the auxiliary alloy casting piece; where the quick-setting casting includes a refining and a casting in sequence.
    Type: Application
    Filed: December 30, 2022
    Publication date: April 18, 2024
    Inventors: Feng XIA, Yulong FU, Chen CHEN, Hailong ZHENG, Zichao WANG, Yonghong LIU, Caina SUN, Yu WANG
  • Publication number: 20240122655
    Abstract: A method for accurately positioning a navigation target point includes: selecting a navigation reference with a fixed position, acquiring positions of the navigation reference and the navigation target point in a navigation coordinate system respectively, and calculating a position of the navigation target point relative to the navigation reference, so as to further obtain a position of the navigation target point in a coordinate system of the navigation reference. As long as the navigation reference does not move, the coordinate system of the navigation reference will not change during the entire navigation process, and spatial position coordinates of the navigation target point in the coordinate system of the navigation reference will not be interfered by the navigation coordinate system.
    Type: Application
    Filed: August 10, 2022
    Publication date: April 18, 2024
    Inventors: Dai FEI, Shunli XU, Xiaopeng GONG, Yu WANG, Fengjie YAO
  • Publication number: 20240126356
    Abstract: The present application discloses a power supply redundancy control system for a GPU server, comprising a power supply redundancy module, a BMC, a CPLD and a GPU module. The power supply redundancy module comprises a first PSU and a second PSU, and the GPU module comprises several GPUs, the first PSU is connected to the CPLD by means of a first bus. The second PSU is connected to the CPLD by means of a second bus. The BMC is connected to the CPLD by means of a first I2C bus and a second I2C bus, and sends heartbeat information to the CPLD. The CPLD is connected to the BMC by means of a third bus and a fourth bus, and the CPLD is connected to the several GPUs by means of a third I2C bus. In the present application, when the BMC is abnormalous or restarted, the CPLD can control the overall power consumption of the server, and can also ensure that the server will not go down, reducing the loss brought to a user due to the BMC being abnormalous or restarted.
    Type: Application
    Filed: January 28, 2022
    Publication date: April 18, 2024
    Inventors: Yue ZHANG, Hongrui HAN, Suhua WANG, Yu LIU
  • Publication number: 20240124455
    Abstract: The present invention is directed to tricyclic compounds, pharmaceutically acceptable compositions comprising compounds of the invention and methods of using said compositions in the treatment of various disorders.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 18, 2024
    Inventors: Ying HAN, Dapeng LI, Huajun LONG, Tong WANG, Zhiyu YIN, Yu WANG
  • Publication number: 20240128089
    Abstract: Embodiments of improved processes and methods that provide selective etching of silicon nitride are disclosed herein. More specifically, a cyclic, two-step dry etch process is provided to selectively etch silicon nitride layers formed on a substrate, while protecting oxide layers formed on the same substrate. The cyclic, two-step dry etch process sequentially exposes the substrate to: (1) a hydrogen plasma to modify exposed surfaces of the silicon nitride layer and the oxide layer to form a modified silicon nitride surface layer and a modified oxide surface layer, and (2) a halogen plasma to selectively etch silicon nitride by removing the modified silicon nitride surface layer without removing the modified oxide surface layer. The oxide layer is protected from etching during the removal step (i.e., step 2) by creating a crystallized water layer on the oxide layer during the surface modification step (i.e., step 1).
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Inventors: Yu-Hao Tsai, Mingmei Wang, Du Zhang
  • Publication number: 20240125850
    Abstract: An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Huiling Zhen, Miaohui Chen, Mingxuan Yuan, Naixing Wang, Wanqian Luo, Yu Huang
  • Publication number: 20240126847
    Abstract: Embodiments of this application provide an authentication method and apparatus, and a storage system. The method includes: receiving a service request sent by a host, where the service request includes a first account, and the first account is an account complying with a first protocol; determining a second account corresponding to the first account, where the second account is an account complying with a target protocol; and authenticating the second account. An account complying with a non-target protocol is mapped to an account complying with the target protocol for unified user permission authentication.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Yu Wang, Wandong Chen, Peng Zhang
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240126716
    Abstract: A systolic array includes a plurality of basic computation units arranged in a matrix. A basic computation includes a feature input register configured to store first feature data, a result buffer configured to store first temporary data, a comparator connected to the feature input register and the result buffer, and a control register connected to the feature input register, the result buffer, and the comparator. The comparator is configured to compare the first feature data input with the first temporary data successively. The control register is configured to control the first feature data of the feature input register and the first temporary data to be input to the comparator, output a comparison result to the result buffer and a feature input register of a next basic computation unit, and after sorting, output the first temporary data last stored in the result buffer as a first data result.
    Type: Application
    Filed: January 24, 2023
    Publication date: April 18, 2024
    Inventors: Yu WANG, Junyuan WU
  • Publication number: 20240130246
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Publication number: 20240130038
    Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 18, 2024
    Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan University
    Inventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20240130104
    Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Fu-Che Lee, Gang-Yi Lin, An-Chi Liu, Yifei Yan, Yu-Cheng Tung
  • Publication number: 20240128867
    Abstract: A system includes: 1) a battery configured to provide an input voltage (VIN); 2) switching converter circuitry coupled to the battery, wherein the switching converter circuitry includes a power switch; 3) a load coupled to an output of the switching converter circuitry; and 4) a control circuit coupled to the power switch. The control circuit includes: 1) a switch driver circuit coupled to the power switch; 2) a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and 3) an analog on-time extension circuit configured to extend an on-time of the power switch by gating a second control signal with the first control signal, wherein the second control signal indicates when to turn the power switch off.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Inventors: Zejing Wang, Zhujun Li, Songming Zhou, Yu Wang
  • Patent number: 11962475
    Abstract: The properties of a plurality of operational units are estimated by generating a central system state graph model representing the properties of the plurality of operational units as probabilities of transitions between states for the plurality of operational units, where the states represent operational data. Then a respective updated system state graph model is generated for each of the plurality of operational units, based on the central system state graph model and based on new operational data for the respective operational unit. A distance measure is determined between the respective updated system state graph models. If the distance measure fulfils a divergence criterion, a plurality of new central system state graph models are generated, each representing the properties of a respective subset of the plurality of operational units as the probabilities of transitions between states for the respective subset of the plurality of operational units.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 16, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Martha Vlachou-Konchylaki, Efthymios Stathakis, Arthur Gusmao, Jörg Niemöller, Swarup Kumar Mohalik, Yu Wang
  • Patent number: 11962535
    Abstract: Method and apparatus for configuring channel characteristics of a reference signal, and a communication device are described. The method includes determining first type signaling, where the first type signaling carries a first type set and the first set includes a plurality of index elements; and sending the first type signaling to a second communication node.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 16, 2024
    Assignee: ZTE Corporation
    Inventors: Bo Gao, Yu Ngok Li, Zhaohua Lu, Yijian Chen, Yifei Yuan, Xinhui Wang
  • Patent number: 11963429
    Abstract: A display module (10) includes: a display panel (12) and a circuit board (14) coupled to the display panel (12). The display panel (12) includes a driving chip (122) and a display unit (124); and the circuit board (14) includes a first filter element (142), wherein the first filter element (142) is coupled to the driving chip (122) and the display unit (124), and a direct current signal output by the driving chip (122) is filtered by the first filter element (142) and then transmitted to the display unit (124). The present disclosure also provides a display apparatus (100).
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 16, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yu Wang, Yi Zhang, Tingliang Liu, Tinghua Shang, Huijuan Yang, Yang Zhou, Pengfei Yu, Linhong Han, Hao Zhang, Xiaofeng Jiang, Huijun Li
  • Patent number: 11959379
    Abstract: Disclosed is a method for measuring gas pressure of a close-distance seam group simultaneously, including the following steps: constructing a pressure-measuring drill hole inclined downwards; lowering a first seam piezometer tube, lowering a baffle and a polyurethane blocking material after a tube head reaching a lowermost seam; and installing a gas pressure gauge; lowering a second seam piezometer tube, lowering the baffle and the polyurethane blocking material after the tube head reaching a second layer of seam; and installing the gas pressure gauge; lowering a nth seam piezometer tube, lowering the baffle and the polyurethane blocking material after the tube head reaching a nth layer of seam; and installing the gas pressure gauge; injecting a high-water and quick-solidifying material into the drill hole; and connecting the gas pressure gauges through optical fibers, and connecting the gas pressure gauges with a ground control system.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: April 16, 2024
    Assignee: Anhui University of Science and Technology
    Inventors: Shaobo Li, Lei Wang, Xingang Niu, Chuanqi Zhu, Zhenyu Yang, Lipeng Chen, Yu Zhang
  • Patent number: 11958038
    Abstract: A group of reductive 2D materials (R2D) with extended reactive vacancies and a method for making the R2D with extended reactive vacancies are provided, especially the example of the reductive boron nitride (RBN). To create defects such as vacancies, boron nitride (BN) powders are milled at cryogenic temperatures. Vacancies are produced by milling, and the vacancies can be used to reduce various metal nanostructures on RBN. Due to the thermal stability of the RBN and the enhanced catalytic performance of metal nanostructures, RBN-metals can be used for different catalysts, including electrochemical catalysts and high temperature catalysts.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 16, 2024
    Assignee: The Penn State Research Foundation
    Inventors: Mauricio Terrones, Yu Lei, He Liu, Kazunori Fujisawa, Ana Laura Elias Arriaga, Tianyi Zhang, Rodolfo Cruz-Silva, Morinobu Endo, Xiaoxing Wang, Cynthia Guerrero-Bermea