Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: A stack including an active layer, a gate dielectric, and a gate electrode is formed in a forward or in a reverse order, over a substrate. The active layer includes a front channel layer, a bulk semiconductor layer, and a back channel layer. The front channel layer is formed by depositing a layer stack that include at least one post-transition metal oxide layer, a zinc oxide layer, and at least one acceptor-type oxide layer. The zinc oxide layer or at least one post transition metal oxide layer contacts the gate dielectric, and the at least one acceptor-type oxide layer is most distal from the gate dielectric. The front channel layer provides enhanced channel conductivity, while the back channel layer provides suppressed channel conductivity.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A multilayer light diffuser plate and a method for manufacturing the same are disclosed. The multilayer light diffusion plate comprises a main layer and a partially-transmissive and partially-reflective layer located under the main layer. The top surface of the main layer is the light-emitting surface, and the light-incident surface is the bottom surface of the partially-transmissive and partially-reflective layer. The partially-transmissive and partially-reflective layer comprises a plurality of first base material layers and a plurality of second base material layers stacked alternately. The materials of the first and second base material layers have different refractive indices. The partially-transmissive and partially-reflective layer formed by alternately stacking the first and second base material layers with different refractive indices is arranged on the light-incident surface of the light diffuser plate by means of extrusion, which is simpler and less expensive to manufacture.

Abstract: The present disclosure provides an interspinous process device. The interspinous process device may include a main body having a cavity formed therein, the main body being configured to be disposed between the two adjacent spinous processes; and a spacer configured to be arranged in the cavity of the main body. When the main body is disposed between the two adjacent spinous processes and the spacer is arranged in the cavity of the main body, a volume of the cavity may be greater than a volume of the spacer, a height of the cavity may be equal to a height of the spacer, and a width of the cavity may be greater than a width of the spacer.

Abstract: A nail product curing system for curing nail products includes a housing having a nail treatment space configured to receive a hand of a user and to position one or more nails of the user, and one or more LED light sources on the housing for generating light in the nail treatment space for performing a curing process. The nail product curing system also includes a sensing and controlling system that includes touchless sensors on the housing configured to sense placement of the hand in the nail treatment space, and to control various parameters of the curing process using movement of the user's hands. The sensing and controlling system also includes a circuit board on the housing and a radio transmission controller in signal communication with the circuit board configured to control the LED light sources and the curing process using programmed instructions.

Abstract: A method, a processing device, and a system for information display are provided, and the system includes a light transmissive display. A first information extraction device extracts spatial position information of a user, and a second information extraction device extracts spatial position information of a target object. The processing device performs the following steps. Display position information of virtual information of the target object on the display is determined according to the spatial position information of the user and the spatial position information of the target object. The display position information includes a first display reference position corresponding to a previous time and a second display reference position corresponding to a current time. An actual display position of the virtual information on the display corresponding to the current time is determined according to a distance between the first display reference position and the second display reference position.

Abstract: Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Abstract: A hand tool rack includes a first housing having a first pivoting portion, a first connecting portion, a first accommodating portion, and a first hanging hole, and a second housing having a second pivoting portion pivotally connected with the first pivoting portion, a second connecting portion, a second accommodating portion, and a second hanging hole. When the second housing is in the closed position, the first accommodating portion is in communication with the second accommodating portion, and the first hanging hole is not aligned with the second hanging hole. When the second housing is in the open position, the first accommodating portion and the second accommodating portion are open toward the same direction, and the first hanging hole is aligned with the second hanging hole.

Abstract: In some embodiments, the present disclosure relates to a memory device that includes gate electrode layers arranged over a substrate. A first memory cell is arranged over the substrate and includes first and second source/drain conductive lines that extend through the gate electrode layers. A barrier structure is arranged between the first and second source/drain conductive lines. A channel layer is arranged on outermost sidewalls of the first and second source/drain conductive lines. A first dielectric layer is arranged between the barrier structure and the channel layer. A memory layer is arranged on sidewalls of the channel layer. The first dielectric layer has a first maximum width measured between outermost sidewalls of the first dielectric layer. The first source/drain conductive line has a second maximum width measured between the outermost sidewalls of the first source/drain conductive line. The second width is greater than the first width.

Abstract: A power conversion system with ripple injection includes an AC-DC conversion unit, a voltage regulation unit, at least one DC-DC conversion unit, at least one load, and a first control unit. The voltage regulation unit provides a DC link and receives one portion of an input power as an energy storage power. Each DC-DC conversion unit receives the other portion of the input power as an output power. The at least one load correspondingly receives the output power for being supplied power. The first control unit is coupled to the DC link, the at least one DC-DC conversion unit, and the at least one load. The first control unit controls the at least one DC-DC conversion unit to adjust a magnitude of a ripple of the output power to perform a ripple injection operation according to a magnitude of a ripple of the input power.

Abstract: A method includes depositing a first work function layer over a first and second gate trench. The method includes depositing a second work function layer over the first work function layer. The method includes etching the second work function layer in the first gate trench while covering the second work function layer in the second gate trench, causing the first work function layer in the first gate trench to contain metal dopants that are left from the second work function layer etched in the first gate trench. The method includes forming a first active gate structure and second active gate structure, which include the first work function layer and the metal dopants left from the second work function layer in the first gate trench, and the first work function layer and no metal dopants left behind from the second work function layer, respectively.

Abstract: The present disclosure provides a method and an electronic apparatus for masking data on an electronic document. The method is performed by the electronic apparatus and includes: displaying the electronic document on a user interface; causing at least one analysis module to perform at least one analysis on the electronic document and a plurality of strings of the electronic document and output a first string among the plurality of strings and first position information associated with the first string according to a result of the at least one analysis; obtaining the first string and the first position information from the at least one analysis module; and generating, based on the first position information and the first string, a first masking object to mask the first string on the electronic document.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

Abstract: A clock control method for a High Definition Multimedia Interface (HDMI) receiver operating in a power-saving mode in a sink device is provided. The HDMI receiver has a first module, a second module, and a third module. The clock control method includes the following stages. A clock signal is enabled to be sent to the first module and the third module during a first region of received data. The clock signal is disabled to be sent to the second module during the first region of the received data. The clock signal is enabled to be sent to the third module and the clock signal is disabled to be sent to the first module and the second module during a second region of the received data.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.

Abstract: The present invention provides a topical composition having a fermented product of lactic acid bacteria synbiotics as an active ingredient. The fermented product of lactic acid bacteria synbiotics is obtained by performing a fermenting step with lactic acid bacteria and a deactivating step on a fermenting substrate. The lactic acid bacteria are consisting of Lactobacillus salivarius subsp. salicinius AP-32, Bifidobacterium animalis subsp. lactis CP-9 and Lactobacillus acidophilus TYCA06. The fermenting substrate includes animal protein, plant protein and/or plant extracts. The aforementioned fermented product of lactic acid bacteria synbiotics can effectively inhibit the growth of Staphylococcus aureus and/or Propionibacterium acnes, and can be used in the topical composition.

Abstract: A light-emitting diode (LED) includes a light-transmissive substrate having a first surface, an epitaxial structure disposed on the first surface, an insulation structure, and first and second electrodes. The epitaxial structure has an upper surface opposite to the first surface, and a side wall interconnecting the upper surface and the first surface. The insulation structure includes a first insulation layer covering the side wall and the upper surface, and a second insulation layer covering a portion of the first surface that is exposed from the epitaxial structure and the first insulation layer. The first insulation layer is formed with first and second holes through which the first and second electrodes are electrically connected to the epitaxial structure. The second insulation layer is formed with an opening. The insulation structure is made of at least one material selected from silicon oxide, silicon nitride, magnesium fluoride, Al2O3, TiO2 and Ti2O5.