Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, and a pair of contact via structures electrically connected to the pair of active regions. The contact via structure is formed in an interlayer dielectric layer that extends over the channel layer.

Abstract: A gas sensor includes a first electrode, a gas detecting layer disposed on the first electrode, and an electric-conduction enhanced electrode unit being electrically connected to the first electrode and the gas detecting layer. The electric-conduction enhanced electrode unit includes an electric-conduction enhancing layer and a second electrode electrically connected to the electric-conduction enhancing layer. The electric-conduction enhancing layer is electrically connected to the gas detecting layer and is made of an electrically conductive organic material.

Abstract: A three-dimensional reflective display device includes a reflective display panel, a lens array disposed on the reflective display panel, and a front light module disposed on the lens array. The reflective display panel includes pixel structures, and each pixel structure includes a left-eye pixel and a right-eye pixel. The lens array includes lenticular lenses extending in a first direction and arranged in a second direction perpendicular to the first direction. The lenticular lenses are respectively corresponding to the pixel structures. The front light module includes two front light components. The two front light components both include a light guide plate and a light source disposed on a light incident surface of the light guide plate, where the light incident surfaces face to each other in the second direction.

Abstract: Methods and systems for performing data correction and phase optimization are disclosed herein. In some implementations, a system for performing data correction comprises: an analog to digital converter (ADC) configured to receive differential data from a continuous time linear equalizer (CTLE) and generate a bitstream comprising a plurality of data bits and a corresponding plurality of data sign bits; a decision feedback equalization (DFE) block configured to receive the bitstream from the ADC and provide data to a clock and data recovery (CDR) block; and data correction circuitry. In some implementations, the data correction circuitry is configured to: receive the bitstream from the ADC; determine whether to correct a data sign bit; responsive to determining the data sign bit is to be corrected, flip the data sign bit; and provide the plurality of data sign bits, including the flipped data sign bits, to the DFE.

Abstract: A mobile device protective case set is suitable for cooperating with a mobile device, the mobile device protective case set includes a main frame and an assembling component, the main frame has an inner circular surface, a back flange and at least one positioning portion, the inner circular surface encloses to define a space, the space is suitable for accommodating the mobile device, the back flange protrudes from the inner circular surface towards the space, the back flange has a device abutting surface, which is suitable for a back side of the mobile device to abut, and the positioning portion is disposed at the device abutting surface; the assembling component has a base portion and at least one clamping portion, the clamping portion is disposed at a partial outer periphery of the base portion, the clamping portion is suitable for combining the positioning portion, and the device abutting surface and the clamping portion are suitable to abut against the back side of the mobile device.

Abstract: A light field display module including a light field display layer, an adjustment layer, and an image forming layer is provided. The light field display layer is configured to form a light field image beam. The adjustment layer is disposed on a path of the light field image beam, and configured to adjust the light field image beam. The image forming layer is disposed on the path of the light field image beam from the adjustment layer, and configured to change a position of a light field image by changing a direction of the light field image beam. The image forming layer has multiple optical micro-structures.

Abstract: An in vitro training method for training genioglossus muscle strength includes adhering an electrode patch of an in vitro training device to a bottom of a chin of a user during a non-sleep period. The electrode patch receives an electrical stimulation signal from an electrical stimulation module of the in vitro training device to stimulate the genioglossus muscle of the user through transdermal electrical stimulation. The electrode patch includes a body surface adhering face and an assembling face opposite to the body surface adhering face. The body surface adhering face is adhered to the bottom of the chin of the user to align with the genioglossus muscle. The electrical stimulation module is disposed on the assembling face and in electrical connection with the electrode patch. The electrical stimulation module sends an electrical stimulation signal to stimulate the genioglossus muscle through transdermal electrical stimulation.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface. A height of the step-height is smaller than a thickness of the first bonding layer.

Abstract: A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Abstract: A semiconductor device includes a first switch, a second switch, a third switch, and a fourth switch formed on a first side of a substrate, wherein the first switch and the second switch are connected in series between a first reference voltage and an output voltage, and wherein the third switch and the fourth switch are connected in series between the first reference voltage and a second reference voltage. The semiconductor device includes a capacitor formed on a second side of the substrate opposite to the first side, and having a first terminal and a second terminal. The first terminal is coupled to a first node between the first and second switches, and the second terminal is coupled to a second node between the third and fourth switches.

Abstract: An in vitro training method includes scanning a user's oral cavity to create a first oral cavity model. An articulator body is selected according to the first oral cavity model, and plural first customized electrode sheets are formed and assembled onto the articulator body to obtain an in vitro training device. The user bites the in vitro training device during a non-sleep period and uses the plural first customized electrode sheets to proceed with electrical stimulation on a top surface and two sides of a tongue of the user, thereby training a muscular endurance of infrahyoid muscles of the user for a training period. The user's oral cavity is scanned again to create a second oral cavity model. The first oral cavity model is compared with the second oral cavity model to timely renew the customized electrode sheets when the image over rate is lower than 80%.

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: The present disclosure relates to a method for producing a component, preferably for a sporting good, comprising the following steps: providing a polymer; providing a solvent; mixing the polymer with the solvent, thereby producing a liquefied polymer; and curing the liquefied polymer, thereby producing the component. Other embodiments of the disclosure relate to an outsole and a sports shoe obtained by the method according to the disclosure.