Patents by Inventor Yu-Wei Lin

Yu-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11587887
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: February 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
  • Patent number: 11575232
    Abstract: The present disclosure provides an electrical plug including a first temperature detection element and a second temperature detection element. When the processor determines that the temperature of the contact pins is greater than or equal to a temperature threshold according to a first detection signal outputted by the first temperature detection element and a second detection signal outputted by the second temperature detection element, the processor disables the electrical plug to transmit the input power to a load. When one of the temperature detection elements fails, the electrical plug determines whether the temperature of the electrical plug is greater than or equal to the temperature threshold according to the other one of the temperature detection elements. The electrical plug meets the redundant design required for functional safety to avoid unexpected hazards caused by the failure of a single temperature detection element. Therefore, the stability of the electrical plug is enhanced.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 7, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Wei Lin, Shao-Hua Li
  • Publication number: 20220360026
    Abstract: The present disclosure provides an electrical plug including a first temperature detection element and a second temperature detection element. When the processor determines that the temperature of the contact pins is greater than or equal to a temperature threshold according to a first detection signal outputted by the first temperature detection element and a second detection signal outputted by the second temperature detection element, the processor disables the electrical plug to transmit the input power to a load. When one of the temperature detection elements fails, the electrical plug determines whether the temperature of the electrical plug is greater than or equal to the temperature threshold according to the other one of the temperature detection elements. The electrical plug meets the redundant design required for functional safety to avoid unexpected hazards caused by the failure of a single temperature detection element. Therefore, the stability of the electrical plug is enhanced.
    Type: Application
    Filed: September 9, 2021
    Publication date: November 10, 2022
    Inventors: Yu-Wei Lin, Shao-Hua Li
  • Patent number: 11489657
    Abstract: Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 1, 2022
    Assignee: Diodes Incorporated
    Inventors: Yu-Wei Lin, Yi Sheng Lin, Nanyuan Chen
  • Publication number: 20220262426
    Abstract: A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.
    Type: Application
    Filed: June 18, 2021
    Publication date: August 18, 2022
    Applicant: National Cheng Kung University
    Inventors: Lih-Yih Chiou, Yu-Wei Lin, Wei-Shuo Ling
  • Publication number: 20220223542
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.
    Type: Application
    Filed: January 14, 2021
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Chun-Yen Lan, Tzu-Ting Chou, Tzu-Shiun Sheu, Chih-Wei Lin, Shih-Peng Tai, Wei-Cheng Wu, Ching-Hua Hsieh
  • Publication number: 20220169347
    Abstract: The present invention discloses a vessel power safety control system and operating method thereof. The vessel power safety control system includes a load power management module, a real-time monitoring module, an integration module and a power module. The present invention can assist the autonomous ship as any occurrence of fault during navigation. Once the accident occurs, the load power management module will give an instruction to control the DC bus to switch from closed circuit to open circuit to protect other equipment. After determining whether the errors of the equipment on board is eliminated, the load power management system performs automatic system reset procedure. As such, the DC bus can be converted from an open circuit to a closed circuit to restart the power supply for the facility.
    Type: Application
    Filed: August 18, 2021
    Publication date: June 2, 2022
    Inventors: BING-XIAN CHEN, HAN-CHUN KAO, HUNG-HSI LIN, YU-WEI LIN, CHUNG-CHING LIN, SHENG-HUA CHEN, HSIAO-YU HSU, WEI-CHUN CHENG
  • Publication number: 20220034342
    Abstract: A fastener is adapted for assembling a first housing to a second housing. The first housing is provided with a protruding portion and a buckling portion, and the second housing has a first surface, a second surface, and a through hole. The fastener includes a first portion, at least one connecting portion, at least two elastic portions, and a second portion. The first portion movably abuts against the first surface and has a first opening. The connecting portion is accommodated in the through hole. One end of the connecting portion is connected to the first portion. The connecting portion is spaced apart from an inner edge of the second housing by a gap. The two elastic portions inclinedly extend into the first opening. The second portion movably abuts against the second surface and is disposed at the another end of the connecting portion.
    Type: Application
    Filed: June 17, 2021
    Publication date: February 3, 2022
    Inventors: JIAN-HUA CHEN, PO-TSUNG SHIH, YU-WEI LIN, MING-HUA HO, CHIH-HAO WU
  • Publication number: 20210366284
    Abstract: An internet of vehicles system for dynamically marking risk area includes a cloud server communicating with a vehicle system. The cloud server includes a communication module, a planning module, a computation module, and a determination module. The communication module is configured to receive vehicle information from the vehicle system. The planning module is configured to formulate a dynamic risk area range according to a vehicle position of the vehicle information. The calculation module is configured to calculate a risk factor coefficient corresponding to the vehicle information and a risk intensity corresponding to the dynamic risk area range. The determination module is configured to determine whether the risk intensity is greater than or equal to a preset threshold value. The communication module notifies a warning to the vehicle system that the risk intensity of the dynamic risk area range is greater than the preset threshold value.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 25, 2021
    Inventors: Yuan-Hsi YEN, Yu-Wei LIN, Min-Chen CHEN
  • Patent number: 11153982
    Abstract: A rollable structure includes an outer and an inner sliding rail. The outer sliding rail includes outer sliding blocks and outer shafts. Each of the outer shafts is fixed between any two adjacent outer sliding blocks. The inner sliding rail is movably clamped in the outer sliding rail and includes inner sliding blocks and inner shafts. Each of the inner shafts is fixed between any two adjacent inner sliding blocks. When axes of the outer shafts are aligned with axes of the inner shafts, the outer sliding blocks can rotate with the outer shafts as axes, and the inner sliding blocks can rotate with the inner shafts as axes. After the inner and the outer sliding rail move relative to each other, the axes of the inner and the outer shafts are misaligned, so that the outer and the inner sliding rail are in a plane.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: October 19, 2021
    Assignee: PEGATRON CORPORATION
    Inventors: Ming-Hua Ho, Yu-Wei Lin, Po-Tsung Shih
  • Publication number: 20210313287
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 11101596
    Abstract: A radio frequency connector includes an outer shell, a connector and a waterproof gasket. The outer shell is provided with partition walls opposite to each other and convex structures protruding toward the partition walls. The first side of the connector is provided with a plurality of plug terminals. The waterproof gasket is disposed surrounding all the plug terminals. When the connector is accommodated in the outer shell, the plug terminal is received corresponding to the through hole of the partition wall. The convex structures abut the second side opposite to the first side to push the connector toward the partition wall for reducing the distance between the first side and the partition wall. Thus, the waterproof gasket can be tightly sandwiched between the first side and the partition wall to enhance the waterproof effect.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 24, 2021
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventor: Yu-Wei Lin
  • Patent number: 11043462
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20210020581
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.
    Type: Application
    Filed: July 17, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
  • Publication number: 20200413555
    Abstract: A rollable structure includes an outer and an inner sliding rail. The outer sliding rail includes outer sliding blocks and outer shafts. Each of the outer shafts is fixed between any two adjacent outer sliding blocks. The inner sliding rail is movably clamped in the outer sliding rail and includes inner sliding blocks and inner shafts. Each of the inner shafts is fixed between any two adjacent inner sliding blocks. When axes of the outer shafts are aligned with axes of the inner shafts, the outer sliding blocks can rotate with the outer shafts as axes, and the inner sliding blocks can rotate with the inner shafts as axes. After the inner and the outer sliding rail move relative to each other, the axes of the inner and the outer shafts are misaligned, so that the outer and the inner sliding rail are in a plane.
    Type: Application
    Filed: May 8, 2020
    Publication date: December 31, 2020
    Inventors: Ming-Hua Ho, Yu-Wei Lin, Po-Tsung Shih
  • Patent number: 10879192
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, an electromagnetic shielding structure enclosing the first semiconductor die and a first portion of the insulating encapsulation, and a redistribution structure. The electromagnetic shielding structure includes a first conductive layer and a dielectric frame laterally covering the first conductive layer. The first conductive layer surrounds the first portion of the insulating encapsulation and extends to cover a first side of the first semiconductor die. The dielectric frame includes a first surface substantially leveled with the first conductive layer.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsaing-Pin Kuan, Ching-Hua Hsieh, Chih-Wei Lin, Chun-Cheng Lin, Yu-Wei Lin, Chun-Yen Lan
  • Publication number: 20190295971
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10319691
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10128195
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10043774
    Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wei Lin, Chen-Shien Chen, Guan-Yu Chen, Tin-Hao Kuo, Yen-Liang Lin