Patents by Inventor Yu-Wei Lin

Yu-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020276
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Patent number: 10014870
    Abstract: A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Wen-Hung Huang, Yu-Wei Lin
  • Patent number: 9966346
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9950021
    Abstract: An anti-cancer active substance from Antrodia Cinnamomea, produced from mycelium of Antrodia Cinnamomea by following steps: (1) culturing mycelium of Antrodia Cinnamomea by liquid fermentation; (2) extracting the thus-obtained mycelium with ethanol and concentrating the extracted solution to obtain an ethanol extract; (3) dissolving the ethanol extract in water, and extracting with equal volume of ethyl acetate to obtain ethyl acetate extract; (4) purifying the ethyl acetate extract by silica gel column chromatography using hexane/ethyl acetate gradient as the mobile phase to obtain an eluate fraction g; and (5) purifying the eluate fraction g by silica gel column chromatography using hexane/ethyl acetate gradient as the mobile phase to obtain a specific eluate fraction which could be purified further to obtain the anti-cancer active substance from Antrodia Cinnamomea.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: April 24, 2018
    Assignee: National Taiwan University
    Inventors: Been-Huang Chiang, Yu-Wei Lin
  • Patent number: 9812405
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20170117245
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Application
    Filed: November 14, 2016
    Publication date: April 27, 2017
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20170053885
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Publication number: 20160365322
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Application
    Filed: August 2, 2016
    Publication date: December 15, 2016
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9508637
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Publication number: 20160336281
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: GUAN-YU CHEN, YU-WEI LIN, TIN-HAO KUO, CHEN-SHIEN CHEN
  • Patent number: 9496233
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9431351
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9425117
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20160240502
    Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Yu-Wei LIN, Chen-Shien CHEN, Guan-Yu CHEN, Tin-Hao KUO, Yen-Liang LIN
  • Publication number: 20160118993
    Abstract: A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Yung-Chow PENG, Wen-Hung HUANG, Yu-Wei LIN
  • Publication number: 20160111378
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: GUAN-YU CHEN, YU-WEI LIN, TIN-HAO KUO, CHEN-SHIEN CHEN
  • Patent number: 9236877
    Abstract: A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that generates a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The first electrical signal is converted to a second electrical signal using a converter coupled between the micro-mechanical structure and the ADC. The first electrical signal is free from being amplified.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Wen-Hung Huang, Yu-Wei Lin
  • Publication number: 20150380332
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20150357301
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: D799454
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 10, 2017
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventor: Yu-Wei Lin