Patents by Inventor Yu-Wei Lin

Yu-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160336281
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Application
    Filed: July 29, 2016
    Publication date: November 17, 2016
    Inventors: GUAN-YU CHEN, YU-WEI LIN, TIN-HAO KUO, CHEN-SHIEN CHEN
  • Patent number: 9496233
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9431351
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9425117
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20160240502
    Abstract: An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Yu-Wei LIN, Chen-Shien CHEN, Guan-Yu CHEN, Tin-Hao KUO, Yen-Liang LIN
  • Publication number: 20160118993
    Abstract: A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Yung-Chow PENG, Wen-Hung HUANG, Yu-Wei LIN
  • Publication number: 20160111378
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: GUAN-YU CHEN, YU-WEI LIN, TIN-HAO KUO, CHEN-SHIEN CHEN
  • Patent number: 9236877
    Abstract: A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that generates a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The first electrical signal is converted to a second electrical signal using a converter coupled between the micro-mechanical structure and the ADC. The first electrical signal is free from being amplified.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Wen-Hung Huang, Yu-Wei Lin
  • Publication number: 20150380332
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20150357301
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9184489
    Abstract: An antenna fixing structure includes an antenna box and a fixing frame. The antenna box includes a casing with a first circumference defined by a first center and a first radius, and the casing has equidistant first connecting portions disposed along the first circumference. The fixing frame includes a carrying board with a second circumference defined by a second center and a second radius, and the carrying board has equidistant second connecting portions disposed along the second circumference, so that the first connecting portions and the second connecting portions can be rotably installed with respect to the first and second centers and coupled to each other. Therefore, the antenna box can be rotated to a predetermined position and then fixed to the fixing frame, and the antenna fixing structure has the effect of adjusting the direction, position or angle of an antenna.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 10, 2015
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventor: Yu-Wei Lin
  • Patent number: 9166287
    Abstract: An antenna sheath includes a tubular member and a base unit. One end of the tubular member is formed with two lateral boards corresponding to each other, an opening is formed between the two lateral boards, each of the lateral boards is formed with a shaft hole, and the inner periphery of at least one of the two shaft holes is formed with at least one first convex tooth; the base unit is installed with a connector inserted in the opening and formed with two lateral surfaces corresponding to each other, the two lateral surfaces are respectively installed with a rotation shaft correspondingly pivoted in the shaft hole, the outer periphery of at least one of the two rotation shafts is formed with plural second convex teeth annularly arranged, and the first convex teeth is engaged between any two of the adjacent second convex teeth.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 20, 2015
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventor: Yu-Wei Lin
  • Patent number: 9161465
    Abstract: In a quick-release fixing structure for an electronic equipment, the electronic equipment includes a plurality of holes and a snap slot, and the quick-release fixing structure includes a substrate, a turning element and a plurality of fixing elements. The substrate includes a plurality of grooves and a port, and each groove includes a first groove hole and a second groove hole interconnected to the first groove hole, and the second groove hole is greater than the first groove hole. The turning element is coupled to the substrate and includes a bump exposed from the port and snapped into the snap slot. Each fixing element is passed through each first groove hole and fixed to each hole. The turning element can be turned to push the electronic equipment to move each fixing element into each second groove hole, and separate the electronic equipment from the substrate.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 13, 2015
    Assignee: GRAND-TEK TECHNOLOGY CO., LTD.
    Inventors: Chia-Jung Chen, Yu-Wei Lin
  • Patent number: 9153550
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Publication number: 20150280307
    Abstract: An antenna fixing structure includes an antenna box and a fixing frame. The antenna box includes a casing with a first circumference defined by a first center and a first radius, and the casing has equidistant first connecting portions disposed along the first circumference. The fixing frame includes a carrying board with a second circumference defined by a second center and a second radius, and the carrying board has equidistant second connecting portions disposed along the second circumference, so that the first connecting portions and the second connecting portions can be rotably installed with respect to the first and second centers and coupled to each other. Therefore, the antenna box can be rotated to a predetermined position and then fixed to the fixing frame, and the antenna fixing structure has the effect of adjusting the direction, position or angle of an antenna.
    Type: Application
    Filed: June 9, 2014
    Publication date: October 1, 2015
    Inventor: Yu-Wei LIN
  • Patent number: 9111817
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: August 18, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Yu Chen, Yu-Wei Lin, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9086718
    Abstract: A key mechanism includes a tray, at least one keycap, at least one supporting structure and an engaging component. The at least one keycap is disposed on a side of the tray. The at least one supporting structure is connected to the tray and the at least one keycap for supporting the at least one keycap on the tray. The engaging component is installed on the tray. The engaging component includes a pivoting portion and an engaging portion. The pivoting portion is pivoted to the at least one supporting structure, and the engaging portion engages into an opening on a casing as the tray is assembled on the casing, so as to fix the tray on the casing.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: July 21, 2015
    Assignee: Wistron Corporation
    Inventor: Yu-Wei Lin
  • Publication number: 20150194379
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.
    Type: Application
    Filed: August 11, 2014
    Publication date: July 9, 2015
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Publication number: 20150162139
    Abstract: A power storage device includes a positive electrode and a negative electrode disposed opposite to the positive electrode. The positive electrode and the negative electrode are respectively disposed on at least one surface of a current collector foil. The positive electrode and the negative electrode respectively include an active material, a conductive auxiliary and an adhesive, wherein the active material includes a porous material, an oxidation-reduction electrode material, or combination thereof. At least one of the positive electrode and the negative electrode has a multilayer structure containing three or more layers. The concentration of the oxidation-reduction electrode material in the outmost layer of the multilayer structure is the lowest.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 11, 2015
    Inventors: Yu-Wei Lin, Li-Duan Tsai, Chia-Chen Fang, Jenn-Yeu Hwang
  • Publication number: 20150130050
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen