Patents by Inventor Yu-Wen Wang

Yu-Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11411094
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 11404426
    Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
  • Publication number: 20220239189
    Abstract: A motor for an electric cylinder includes a motor body, an encoder, a rotor coupling portion and an encoder fixing portion. The motor body includes a rotor having a shaft hole through which a rotating shaft extends. The encoder is installed on the motor body and includes a fixing ring fixed on the rotating shaft, a magnet holder combined with the fixing ring, an encoder magnet mounted on the magnet holder, and a magnetic sensor opposite to the encoder magnet. The magnet holder is rotatable relative to the fixing ring to adjust the magnetic pole position of the encoder magnet relative to the magnetic sensor. The rotor coupling portion is arranged on the rotor and fixed to the rotating shaft at a first corresponding position. The encoder fixing portion is arranged on the fixing ring and fixed with the rotating shaft at a second corresponding position.
    Type: Application
    Filed: October 12, 2021
    Publication date: July 28, 2022
    Inventors: Kun-Cheng Tseng, Hao-Wen Tseng, Yu-Li Wang, Po-Tsao Yang
  • Publication number: 20220228257
    Abstract: In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Chi-Cheng HUNG, Pei-Wen WU, Yu-Sheng WANG, Pei-Shan CHANG
  • Patent number: 11393815
    Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11390845
    Abstract: Provided is a method for manufacturing cell-containing blocks having steps of: preparing an standardized size mold by 3D printing (three dimensional printing) using a biocompatible elastic material; injecting a thermosensitive colloid into the mold to form a thermosensitive mold; injecting a hydrogel containing cells in to the thermosensitive mold and curing the hydrogel containing cells to form the cell-containing blocks; separating the thermosensitive mold and the cell-containing blocks at a temperature higher than a solidifying point of the thermosensitive colloid. Also provided are method for assembling the cell-containing blocks in a target configuration by using an assembling mold defining the target configuration and made of a thermoreversible material.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 19, 2022
    Assignee: Asia University
    Inventors: Yu Fang Shen, Ming You Shie, Yi Wen Chen, Wei Huang Wang
  • Publication number: 20220223606
    Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen SU, Yu-Kuan LIN, Shih-Hao LIN, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 11387109
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu, deseased
  • Patent number: 11335589
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 11316030
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220119616
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Applicant: NOVOLOOP, INC.
    Inventors: Jia Yun YAO, Yu Wen WANG, Tapaswy MUPPANENI, Ruja SHRESTHA, Jennifer LE ROY, Garret D. FIGULY
  • Publication number: 20220083028
    Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.
    Type: Application
    Filed: January 4, 2021
    Publication date: March 17, 2022
    Inventors: YU-WEN WANG, Jia-Hua Hong
  • Publication number: 20220045199
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20220043027
    Abstract: A probe module includes a circuit board and at least one probe formed on a probe installation surface of the circuit board by a microelectromechanical manufacturing process and including a probe body and a probe tip. The probe body includes first and second end portions and a longitudinal portion having first and second surfaces facing toward opposite first and second directions. The probe tip extends from the probe body toward the first direction and is processed with a gradually narrowing shape by laser cutting. The first and/or second end portion has a supporting seat protruding from the second surface toward the second direction and connected to the probe installation surface, such that the longitudinal portion and the probe tip are suspended above the probe installation surface. The probe has a tiny pinpoint for detecting tiny electronic components, and its manufacturing method is time-saving and high in yield rate.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 10, 2022
    Applicant: MPI CORPORATION
    Inventors: Yu-Chen HSU, Bang-Shun LIU, Ming-Ta HSU, Fuh-Chyun TANG, Shao-Lun WEI, Ya-Fan KU, Yu-Wen WANG
  • Patent number: 11220586
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 11, 2022
    Assignee: Novoloop, Inc.
    Inventors: Jia Yun Yao, Yu Wen Wang, Tapaswy Muppaneni, Ruja Shrestha, Jennifer Le Roy, Garret D. Figuly
  • Publication number: 20210403069
    Abstract: The present invention provides a baby stroller frame linked folding device. A linked folding joint is provided on the upper end of a rear leg frame and is pivotally connected with a front leg frame and a handlebar frame. The handlebar frame comprises a lower handlebar frame that is pivotally connected to the linked folding joint, a handlebar folding clutch joint configured on the upper end of the lower handlebar frame, and an upper handlebar frame pivotally connected to the handlebar folding clutch joint.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Yu-Wen Wang, Sheng-Po Hung
  • Publication number: 20210391449
    Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Ssu-Yu Liao, Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11192999
    Abstract: This invention relates to the field of plastic waste decomposition. More specifically, the invention comprises products obtained from the decomposition of plastic waste.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 7, 2021
    Assignee: Novoloop, Inc.
    Inventors: Jia Yun Yao, Yu Wen Wang, Tapaswy Muppaneni, Ruja Shrestha, Jennifer Le Roy, Garret D. Figuly
  • Patent number: 11158726
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20210257479
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: September 15, 2020
    Publication date: August 19, 2021
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu