Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Abstract: A method for fabrication of a semiconductor structure according to some embodiments of the present disclosure comprises following steps. A first mandrel is formed over a target layer over a substrate, wherein the first mandrel comprises a mandrel island connecting a first mandrel strip and a second mandrel strip. A first spacer is formed along first and second sidewalls of the mandrel island, the first mandrel strip, and the second mandrel strip. The first mandrel is then removed, and the target layer is patterned with the first spacer remains over the target layer. The first mandrel strip and the second mandrel strip are misaligned from one another.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

Abstract: A method for fabricating a semiconductor device includes forming a fin structure that includes a plurality of semiconductor channel layers alternatively spaced apart from one another with a plurality of semiconductor sacrificial layers. The method further includes forming a semiconductor cladding layer extending along sidewalls of the fin structure. The method further includes patterning the semiconductor cladding layer to have a top surface with a highest point and a lowest point by performing at least one sequential combination of a first etching process and a second etching process. A vertical difference between the highest point and the lowest point is less than 3 nanometers.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Abstract: A semiconductor device includes a first channel structure extending along a first lateral direction and a second channel structure extending along the first lateral direction. The second channel structure is spaced apart from the first channel structure. The semiconductor device further includes a high-k dielectric structure extending along the first lateral direction and disposed between the first and second channel structures. The high-k dielectric structure has a bottom surface that comprises a bottommost portion and at least a first plateau portion elevated from the bottommost portion.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.

Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.

Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A probe module includes a circuit board and at least one probe formed on a probe installation surface of the circuit board by a microelectromechanical manufacturing process and including a probe body and a probe tip. The probe body includes first and second end portions and a longitudinal portion having first and second surfaces facing toward opposite first and second directions. The probe tip extends from the probe body toward the first direction and is processed with a gradually narrowing shape by laser cutting. The first and/or second end portion has a supporting seat protruding from the second surface toward the second direction and connected to the probe installation surface, such that the longitudinal portion and the probe tip are suspended above the probe installation surface. The probe has a tiny pinpoint for detecting tiny electronic components, and its manufacturing method is time-saving and high in yield rate.