Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.

Abstract: A semiconductor structure includes a first electrode comprising a first metallic material; a memory film including at least one dielectric metal oxide material and contacting the first electrode; and a second electrode comprising a second metallic material and contacting the memory film. The memory film includes a center region having a first average atomic ratio of a passivation element to oxygen that is less than 0.01, and includes a peripheral region having a second average atomic ratio of the passivation element to oxygen that is greater than 0.05.

Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. The thin-film circuitry may be formed in thin-film transistor (TFT) layers and the organic light-emitting diodes may include anodes and cathodes and an organic emissive layer formed over the TFT layers between the anodes and cathodes. The organic emissive layer may be formed via chemical evaporation techniques. The display may include moisture blocking structures such as organic emissive layer disconnecting structures that introduce one or more gaps in the organic emissive layer during evaporation so that any potential moisture permeating path from the display panel edge to the active area of the display is completely terminated.

Abstract: Video encoding or decoding methods and apparatuses include receiving input data associated with a current block in a current picture, determining a preload region in a reference picture shared by two or more coding configurations of affine prediction or motion compensation or by two or more affine refinement iterations, loading reference samples in the preload region, generating predictors for the current block, and encoding or decoding the current block according to the predictors. The predictors associated with the affine refinement iterations or coding configurations are generated based on some of the reference samples in the preload region.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

Abstract: For each prediction candidate of a set of one or more prediction candidates of the current block, a video coder computes a matching cost between a set of reference pixels of the prediction candidate in a reference picture and a set of neighboring pixels of a current block in a current picture. The video coder identifies a subset of the reference pictures as major reference pictures based on a distribution of the prediction candidates among the reference pictures of the current picture. A bounding block is defined for each major reference picture, the bounding block encompassing at least portions of multiple sets of reference pixels for multiple prediction candidates. The video coder assigns an index to each prediction candidate based on the computed matching cost of the set of prediction candidates. A selection of a prediction candidate is signaled by using the assigned index of the selected prediction candidate.

Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: A radar detection and identification device is disclosed, comprising at least one display host, at least one camera and at least one radar detector, wherein the camera and the radar detector, after photographing and detecting, are capable of performing masked face recognition and radar physiological detection recognition processes in order to identify the identity information and human physiological signals and display them on the display host.

Abstract: Low-latency video coding methods and apparatuses include receiving input data associated with a current Intra slice composed of Coding Tree Units (CTU), where each CTU includes luma and chroma Coding Tree Blocks (CTBs), partitioning each CTB into non-overlapping pipeline units, and encoding or decoding the CTUs in the current Intra slices by performing processing of chroma pipeline units after beginning processing of luma pipeline units in at least one pipeline stage. Each of the pipeline units is processed by one pipeline stage after another pipeline stage, and different pipeline stages process different pipeline units simultaneously. The pipeline stage in the low-latency video coding methods and apparatuses simultaneously processes one luma pipeline unit and at least one previous chroma pipeline unit within one pipeline unit time interval.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Abstract: A system for monitoring a helium compressor and a magnetic resonance imaging device may include photoelectric converter configured to monitor a status current of a helium compressor; a dry contact signal converter having a dry contact switch and a signal converter. The dry contact switch may include a first pair of switch contacts connected to an output of the photoelectric converter and a second pair of switch contacts connected to an output voltage of the helium compressor. The signal converter may be configured to collect an action signal of the dry contact switch, and convert corresponding fault information into a network signal and send the same to a network server. Personnel may be notified of the fault information in a preset communication mode using a preset communication address.

Abstract: Conventional intra-prediction uses pixels from left and upper neighbour blocks to predict a macroblock (MB). Thus, the MBs must be sequentially processed, since reconstructed left and upper MBs must be available for prediction. In an improved method for encoding Intra predicted MBs, a MB is encoded in two steps: first, a first portion of the MB is encoded independently, without references outside the MB. Pixels of the first portion can be Intra predicted using DC mode. Then, the first portion is reconstructed. The remaining pixels of the MB, being a second portion, are intra predicted from the reconstructed pixels of the first portion and then reconstructed. The first portion comprises at least one column or one row of pixels of the MB. The encoding is applied to at least two Intra predicted MBs per slice, or per picture if no slices are used.

Abstract: According to a method for Adaptive Loop Filter (ALF) processing of reconstructed video, multiple indicators are signaled in slice at an encoder side or parsed at a decoder side, where the multiple indicators are Adaptive Parameter Set (APS) indices associated with temporal ALF filter sets for the ALF processing. A current indicator is determined from the multiple indicators, where the current indicator is used to select a current ALF filter set. Filtered-reconstructed pixels are derived for the current block by applying the current ALF filter to the current block. In another method, if the ALF processing applied at a target sample requires an outside sample on other side of a target virtual boundary from the target sample, the outside sample is replaced by a padded sample.

Abstract: Methods and apparatus for video coding system utilizing Rate-Distortion Optimized Quantization (RDOQ) are provided. According to one method, a rate for a level belonging to a level set of a current quantized transform coefficient is estimated for a current coefficient group (CG) based on neighboring quantized coefficients of the current quantized transform coefficient and the current CG. A best level for the current quantized transform coefficient is selected from the level set for a best RD-cost. In another method, a TB is partitioned into M regions and M best regions are derived for the M regions according to RDOQ. At least two alternative region RD-costs are generated for each of the M best regions based on a relative position between each of the M best regions and a last significant region in the TB. TB RD-cost for the TB is selected according a last non-zero best region position.

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Abstract: Various schemes for realizing JCCR mode decision in frequency domain are described. An apparatus receives first and second pixel data of a current block of a picture and transform the pixel data into first and second transformed data in frequency domain. The apparatus generates joint pixel data comprising a pixelwise linear combination of the first and second transformed data. The apparatus generates reconstructed joint pixel data based on the joint pixel data by quantization and inverse quantization operations. The apparatus derives first and second reconstructed pixel data based on the reconstructed joint pixel data. The apparatus accordingly calculates first and second distortion values in frequency domain, based on which a preferred mode may be determined to code the current block.