Abstract: A method for performing transform skip mode (TSM) in a video decoder is provided. A video decoder receives data from a bitstream to be decoded as a plurality of video pictures. The video decoder parses the bitstream for a first syntax element in a sequence parameter set (SPS) of a current sequence of video pictures. When the first syntax element indicates that transform skip mode is allowed for the current sequence of video pictures and when transform skip mode is used for a current block in a current picture of the current sequence, the video decoder reconstructs the current block by using quantized residual signals that are not transformed.

Abstract: Method and apparatus of Inter prediction for video coding are disclosed. When a sub-block motion compensation coding tool is selected for the current block, the method generates sub-block MVs (motion vectors) associated with multiple sub-blocks, which are included or contained in the current block, according to the sub-block motion compensation coding tool, constrains the sub-block MVs within a range to form constrained sub-block MVs, and applies motion compensation to the current block using the constrained sub-block MVs or applies motion compensation to the current block using one sub-block MV within the range around the primary MV in a second list if a corresponding sub-block MV in a first list is outside the range. In another method, motion compensation is applied to the current block only using reference pixels of reference sub-blocks within a primary reference block.

Abstract: The present disclosure provides a DC motor driving system including a DC motor, a power supply device, a switch circuit, and a microprocessor. The power supply device provides an input electrical energy. The switch circuit receives the input electrical energy and outputs a motor electrical energy, which includes a motor power and a motor voltage, to the DC motor. The DC motor driving system switchably works in a constant-voltage mode, a first variable-voltage mode, or a second variable-voltage mode. In the constant-voltage mode, the input electrical energy remains unchanged. In the first variable-voltage mode, the microprocessor controls the power supply device to adjust the input electrical energy for increasing the motor voltage and the motor power. In the second variable-voltage mode, the microprocessor controls the power supply device to adjust the input electrical energy for decreasing the motor voltage and keeping the motor power unchanged.

Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream determines a block boundary of the current block and sub-block boundaries inside the current block, wherein the current block is partitioned into a plurality of sub-blocks using sub-block mode prediction. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a current filtered-reconstructed block, wherein said applying the de-blocking process to the current block comprises applying the de-blocking process to the sub-block boundaries inside the current filtered-reconstructed block, and generates a filtered decoded picture including the current filtered-reconstructed block.

Abstract: Methods and apparatus of motion compensation using the bi-directional optical flow (BIO) techniques are disclosed. According to one method of the present invention, the BIO process is applied to encode or decode bi-directional current block in Merge mode only or in AMVP (advanced motion vector prediction) mode only. According to another method, the BIO process conditionally to encode or decode the current block depending on a jointly-coded flag if the current block is coded using a bi-prediction mode. According to yet another method, x-offset value vx and y-offset value vy for the current block are added to the current motion vector to form a final motion vector. The final motion vector is then used as a reference motion vector for following blocks. In still yet another method, the BIO process is applied to the chroma component.

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

Abstract: The light device with integrated scent atomization module includes a lighting module, a scent atomization module, and an airflow module. The lighting module includes a lighting element producing light, a socket element to a side of the lighting element, and a cap element to a side of the socket element. The scent atomization module is detachably joined to the socket element, and includes an atomizer, and a container adjacent to the atomizer. The airflow module is configured inside the lighting module. The composite lighting device can be mounted to an ordinary lamp socket and substituted for an ordinary light bulb. Through the scent atomization module's atomization of the essential oil stored in the container, scent is released outside of the composite lighting device to achieve air purification. The heat from the lighting element may also accelerate and make more fully the atomization of the scent atomization module.

Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.

Abstract: A resistive memory device includes an ultrathin barrier layer disposed between the bottom electrode and the bottom electric contact to the memory device. The ultrathin barrier layer may reduce the overall step height of the resistive memory elements by 15% or more, including up to about 20% or more. The use of an ultrathin barrier layer may additionally improve the uniformity of the thickness of the dielectric etch stop layer that partially underlies and extends between the memory elements by at least about 15%. The use of an ultrathin barrier layer may result in improved manufacturability and provide reduced costs and higher yields for resistive memory devices, and may facilitate integration of resistive memory devices in advanced technology nodes.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.

Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Abstract: Methods and apparatus for in-loop processing of reconstructed video are disclosed. According to one method, a virtual boundary is determined for to-be-processed pixels in the current picture, where the virtual boundary is aligned with block boundaries and at least one to-be-processed pixel on a first side of the virtual boundary requires one or more second pixels on a second side of the virtual boundary. According to the method, the in-loop processing is modified if a target to-be-processed pixel requires at least one second pixel from the second side of the virtual boundary and the modified in-loop processing eliminates the need for any second pixel on the second side of the virtual boundary. According to another method, the operations of block classification are changed when part of the required pixels in one 10×10 window used in classification are at the other side of virtual boundaries.

Abstract: Video encoding methods and apparatuses for Sum of Absolute Transformed Difference (SATD) computation by folded Hadamard transform circuits include splitting a current block into SATD blocks, receiving input data associated with a first block of a first SATD block in a first cycle and receiving input data associated with a second block of the first SATD block in a second cycle, and performing calculations for the first block by shared Hadamard transform circuits in the first cycle and performing calculations for the second block by the shared Hadamard transform circuits in the second cycle. Each shared Hadamard transform circuit is a first part of each folded Hadamard transform circuit. The video encoding methods and apparatuses further perform calculations for the entire SATD block by a final part of each folded Hadamard transform circuit to generate a final SATD result of the first SATD block for encoding.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.

Abstract: A cooling system for a heat-generating electronic device includes a cold plate module, a flow channel, and a fin arrangement. The cold plate module includes a base plate and a top cover. The flow channel is for a liquid coolant and extends between an inlet connector and an outlet connector. The liquid coolant flows along a flow direction. The fin arrangement is located between the base plate and the top cover. The fin arrangement is thermally coupled to the flow channel and is eccentrically located relative to the cold plate module.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

Abstract: A manufacturing method of a semiconductor device is provided in an embodiment of the present invention. The manufacturing method includes the following steps. A transistor is formed on a substrate. The transistor includes a plurality of semiconductor sheets and two source/drain structures. The semiconductor sheets are stacked in a vertical direction and separated from one another. Each of the semiconductor sheets includes two first doped layers and a second doped layer disposed between the two first doped layers in the vertical direction. A conductivity type of the second doped layer is complementary to a conductivity type of each of the two first doped layers. The two source/drain structures are disposed at two opposite sides of each of the semiconductor sheets in a horizontal direction respectively, and the two source/drain structures are connected with the semiconductor sheets.