Patents by Inventor Yu Wen

Yu Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979593
    Abstract: Method and apparatus for affine CPMV or ALF refinement are mentioned. According to this method, statistical data associated with the affine CPMV or ALF refinement are collected over a picture area. Updated parameters for the affine CPMV refinement or the ALF refinement are then derived based on the statistical data, where a process to derive the updated parameters includes performing multiplication using a reduced-precision multiplier for the statistical data. The reduced-precision multiplier truncates at least one bit of the mantissa part. In another embodiment, the process to derive the updated parameters includes performing reciprocal for the statistical data using a lookup table with (m?k)-bit input by truncating k bits from the m-bit mantissa part, and contents of the lookup table includes m-bit outputs. m and k are positive integers.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: May 7, 2024
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chun Chiu, Tzu-Der Chuang, Ching-Yeh Chen, Chun-Chia Chen, Chih-Wei Hsu, Yu-Wen Huang
  • Patent number: 11980041
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20240143880
    Abstract: A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.
    Type: Application
    Filed: January 27, 2023
    Publication date: May 2, 2024
    Inventors: Yu-Wen LIN, Bogdan TUTUIANU, Florentin DARTU, Wei-Chih HSIEH, Osamu TAKAHASHI
  • Patent number: 11973985
    Abstract: Various schemes pertaining to pre-encoding processing of a video stream with motion compensated temporal filtering (MCTF) are described. An apparatus determines a filtering interval for a received raw video stream having pictures in a temporal sequence. The apparatus selects from the pictures a plurality of target pictures based on the filtering interval, as well as a group of reference pictures for each target picture to perform pixel-based MCTF, which generates a corresponding filtered picture for each target picture. The apparatus subsequently transmits the filtered pictures as well as non-target pictures to an encoder for encoding the video stream. Subpictures of natural images and screen content images are separately processed by the apparatus.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 30, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Yao Chiu, Chun-Chia Chen, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Patent number: 11967906
    Abstract: A hybrid power conversion circuit includes a high-side switch, a low-side switch, a transformer, a resonance tank, a first switch, a second switch, a first synchronous rectification switch, a second synchronous rectification switch, and a third switch. The resonance tank has an external inductor, an external capacitance, and an internal inductor. The first switch is connected to the external inductor. The second switch and a first capacitance form a series-connected path, and is connected to the external capacitance. The first and second synchronous rectification switches are respectively coupled to a first winding and a second winding. The third switch is connected to the second synchronous rectification switch. When an output voltage is less than a voltage interval, the hybrid power conversion circuit operates in a hybrid flyback conversion mode, and otherwise the hybrid power conversion circuit operates in a resonance conversion mode.
    Type: Grant
    Filed: October 11, 2022
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sheng-Yu Wen, Cheng-Yi Lin, Ting-Yun Lu
  • Publication number: 20240120317
    Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.
    Type: Application
    Filed: July 13, 2023
    Publication date: April 11, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
  • Patent number: 11956421
    Abstract: Method and apparatus of video coding are disclosed. According to one method, in the decoder side, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block when the neighboring block satisfies one or more conditions. An MPM (Most Probable Mode) list is derived based on information comprising at least one of neighboring Intra modes. A current Intra mode is derived utilizing the MPM list. The current luma block is decoded according to the current Intra mode According to another method, a predefined Intra mode is assigned to a neighboring block adjacent to the current luma block if the neighboring block is coded in BDPCM (Block-based Delta Pulse Code Modulation) mode, where the predefined Intra mode is set to horizontal mode or vertical mode depending on prediction direction used by the BDPCM mode.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 9, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang, Shih-Ta Hsiang
  • Patent number: 11952467
    Abstract: A method for processing a polyalkylene benzenedicarboxylate material includes subjecting a polyalkylene benzenedicarboxylate material to an immersion treatment with an immersion liquid including ethylene glycol, so as to obtain an immersed polyester material, and subjecting the immersed polyester material to a disintegration treatment to obtain a disintegrated polyester material. The immersed polyester material has crystallinity higher than that of the polyalkylene benzenedicarboxylate material.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: April 9, 2024
    Assignee: National Taiwan University
    Inventors: Chia-Wen Wu, Wei-Sheng Liao, Yu-Wen Chiao
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Publication number: 20240114116
    Abstract: A multi-projector system and a method of calibrating the multi-projector system are provided. The method includes: controlling a first projector to project a first image, and capturing and generating a first captured image including the first image to obtain a first color value from the first captured image through an image capturing device; projecting a second image according to a first projection parameter, and capturing and generating a second captured image including the second image to obtain a second color value from the second captured image through the image capturing device, wherein the first projection parameter includes an electrical parameter of a light source module of the second projector; calculating an absolute difference between the first color value and the second color value; and adjusting the first projection parameter to update the absolute difference in response to the absolute difference being greater than a first threshold.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Applicant: Coretronic Corporation
    Inventors: Xuan-En Fung, Chun-Lin Chien, Yu-Wen Lo, Yu-Hua Yang
  • Patent number: 11945918
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 2, 2024
    Assignee: Novoloop, Inc.
    Inventors: Jia Yun Yao, Yu Wen Wang, Tapaswy Muppaneni, Ruja Shrestha, Jennifer Le Roy, Garret D. Figuly
  • Publication number: 20240098527
    Abstract: This document describes improvements in range and reliability for wireless mesh networks implementing IEEE 802.11 networking technologies. Reducing the number of spatial streams, N, to a lower value at middle and far distance ranges using an optimized rate control algorithm, preemptively trades off a lower throughput limit for a higher link budget. This higher link budget provides longer range and higher RF link reliability by using an N×N spatial diversity of MIMO RF channels for maximizing link budget instead of network throughput.
    Type: Application
    Filed: February 4, 2022
    Publication date: March 21, 2024
    Applicant: Google LLC
    Inventors: Yu Wen, Zhifeng Cai, Srinivasa Kumar Duvvuri, Raymond Reynolds Hayes, Kevin N. Hayes, Der-Woei Wu
  • Publication number: 20240094783
    Abstract: An example computing device includes a first housing portion, a second housing portion moveably connected to the first housing portion, a link to selectively secure the second housing portion to the first housing portion to inhibit movement of the second housing portion relative to the first housing portion, and a shape-memory alloy element to release the link to allow the second housing portion to move relative to the first housing portion.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Yu-Wen LIN, Chia-Ming TSAI, Shih-Jen CHOU, John Joseph GRODEN
  • Publication number: 20240096641
    Abstract: Exemplary methods of semiconductor processing may include etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The first portion of the feature may at least partially extend through one or more layers of material formed on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include generating plasma effluents of the carbon-containing precursor. The methods may include contacting the substrate with the plasma effluents of the carbon-containing precursor. The methods may include forming a carbon-containing material on the substrate. The carbon-containing material may line the first portion of the feature at least partially extending through the one or more layers of material formed on the substrate. The carbon-containing material may be formed in the same chamber where the feature is etched.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Hailong Zhou, Iljo Kwak, Olivier P. Joubert, Yu Wen
  • Patent number: 11924444
    Abstract: Method and apparatus for constrained de-blocking filter are disclosed. One method receives input data related to a current block in a current picture at a video encoder side or a video bitstream corresponding to compressed data including the current block in the current picture at a video decoder side, and determines a first boundary associated with the current block, wherein the first boundary corresponds to one vertical boundary or one horizontal boundary of the current block. The method then applies de-blocking process to a reconstructed current block corresponding to the current block to result in a filtered-reconstructed current block, using a plurality of first reference samples at a same side of the first boundary, and replaces a first set of the first reference samples by one or more padding values. The method then generates a filtered decoded picture including the filtered-reconstructed current block.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 11923437
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Patent number: 11917185
    Abstract: A method and apparatus of Inter prediction for video coding using Multi-hypothesis (MH) are disclosed. If an MH mode is used for the current block: at least one MH candidate is derived using reduced reference data by adjusting at least one coding-control setting; an Inter candidate list is generated, where the Inter candidate list comprises said at least one MH candidate; and current motion information associated with the current block is encoded using the Inter candidate list at the video encoder side or the current motion information associated with the current block is decoded at the video decoder side using the Merge candidate list. The coding control setting may correspond to prediction direction setting, filter tap setting, block size of reference block to be fetched, reference picture setting or motion limitation setting.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 27, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Man-Shu Chiang, Chih-Wei Hsu, Tzu-Der Chuang, Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20240061917
    Abstract: A driving record authentication method is provided. The method includes acquiring historical driving records of a driver and associated records of the driver. Once a non-fungible token image of the driver is minted based on the historical driving records and the associated records, the non-fungible token image is transmitted to a user terminal in response to a query request associated with the driver that sent the user terminal.
    Type: Application
    Filed: October 25, 2022
    Publication date: February 22, 2024
    Inventors: SHIH CHUN WANG, YU-WEN CHEN, SHIH-YIN TSENG, TING-YU DU
  • Patent number: D1015605
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 20, 2024
    Inventor: Yu Wen