Patents by Inventor Yu Yuan

Yu Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563589
    Abstract: A certificate management system includes an electronic device and a server. The electronic device is configured to transmit a certificate application request. The server is configured to sign a device certificate corresponding to the electronic device through an intermediate certificate device after receiving the certificate application request, and transmit the device certificate and the Internet address of the server to the electronic device. The electronic device stores the device certificate and the Internet address of the server to complete the certificate issuance operation.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 24, 2023
    Assignee: MOXA INC.
    Inventors: Chi-Yuan Kao, Yu-Chen Kao, Hung-Chun Chen, Chih-Hsiung Shih
  • Publication number: 20230016518
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Inventors: Yu-Chung LIEN, Abhijith PRAKASH, Keyur PAYAK, Jiahui YUAN, Huai-Yuan TSENG, Shinsuke YADA, Kazuki ISOZUMI
  • Publication number: 20230017727
    Abstract: A light-emitting device includes a semiconductor light-emitting stack, first and second electrodes, an insulating layer, and a passivation layer. Each of the first and second electrodes is disposed on the semiconductor light-emitting stack. The insulating layer at least partially covers the semiconductor light-emitting stack. The passivation layer is disposed on the insulating layer, and covers the semiconductor light-emitting stack and a side surface of each of the first and second electrodes, to expose an upper surface of each of the first and second electrodes. The first electrode and the second electrode are separated by a distance that is greater than 0 ?m and that is not greater than 80 ?m.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Inventors: SU-HUI LIN, YU-CHIEH HUANG, FENG WANG, ANHE HE, QING WANG, XIUSHAN ZHU, KANG-WEI PENG, LING-YUAN HONG
  • Patent number: 11555598
    Abstract: A ceiling fan light kit and a ceiling fan connecting module are provided. The ceiling fan light kit includes the ceiling fan connecting module, a light board, and a light cover module. The ceiling fan connecting module includes a mounting plate and a base. The mounting plate has a plurality of arc holes, a plurality of rotary fixing structures, and a plurality of backstop structures, and a placing hole and a fixing hole are respectively formed at two ends of each of the arc holes. The mounting plate has one of the rotary fixing structures and one of the backstop structures that are spaced apart from one another formed at two sides of each of the arc holes. The base has a bottom plate, a cooling portion, and a plurality of dowels that are respectively disposed in the placing holes.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: January 17, 2023
    Assignee: HOTECK INC.
    Inventors: Kai-Jen Tsai, Yu-Ting Ting, Chia-Wei Chang, Min-Yuan Hsiao
  • Patent number: 11555737
    Abstract: Herein disclosed is an optoelectronic measuring device. The optoelectronic measuring device comprises an objective lens, an imaging lens, a camera, and an optical path adjusting module which are disposed at the first light path. The objective lens receives a first testing light, and transforms the first testing light into a second testing light. The imaging lens receives the second testing light, and transforms the second testing light into a third testing light. The camera measures a beam characteristic of the third testing light. The optical path adjusting module, disposed between the imaging lens and the camera, comprises a mirror, the mirror moves relatively to the imaging lens according to a test command, and adjusts the distance between the imaging lens and the camera at the first light path to be a first optical distance or a second optical distance. Wherein the mirror reflects the third testing light vertically.
    Type: Grant
    Filed: May 24, 2020
    Date of Patent: January 17, 2023
    Assignee: CHROMA ATE INC.
    Inventors: Yu-Yen Wang, Kuo-Wei Huang, Szu-Yuan Weng
  • Publication number: 20230012045
    Abstract: A method for Co-Reception (Co-Rx) operation of multiple transceiver radios sharing the same antenna and Low Noise Amplifier (LNA) is provided. A first receiver radio of a wireless communication device determines the first gain mode of an LNA based on the first signal indicator. A second receiver radio of the wireless communication device determines the second gain mode of the LNA based on the second signal indicator. The LNA is shared by the first receiver radio and the second receiver radio and is coupled to an antenna. A Packet Traffic Arbitration (PTA) circuitry of the wireless communication device configures the LNA to operate in the first gain mode or the second gain mode based on the priority levels of the first receiver radio and the second receiver radio.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 12, 2023
    Inventors: Li-Wei CHEN, Tsai-Yuan HSU, Chen-Feng LIU, Wen-Ying CHIEN, Chia-Hung HSU, Yu-Lin TSAI
  • Publication number: 20230003956
    Abstract: A semiconductor package structure and a method of manufacturing the same are provided. A semiconductor package structure includes a first electronic component and a light emitter. The photonic component includes a substrate and a first port. The light emitter is disposed over the substrate of the photonic component. The light emitter is configured to emit light through the first port. A coupling loss between the first port of the photonic component and the light emitter is less than 3 dB.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Feng YOU, Yu-Yuan YEH, Jun-Wei CHEN
  • Publication number: 20230002938
    Abstract: The present disclosure relates to an elastic fiber, an elastic fiber covered yarn and reeling manufacturing methods thereof The reeling manufacturing method of an elastic fiber includes: providing an elastic fiber material, the elastic fiber material having a core portion and a skin portion, the skin portion covering the core portion; performing a first extending, to have the elastic fiber material passing a first guiding roller, the speed of the first guiding roller being 500-1500 m/min; performing a second extending, to have the elastic fiber material passing a second guiding roller, the speed of the second guiding roller being 1200-2400 m/min; and performing a third extending, to have the elastic fiber material passing a third guiding roller, the speed of the third guiding roller is 1300-2600 m/min.
    Type: Application
    Filed: June 28, 2022
    Publication date: January 5, 2023
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, LI-YUAN CHEN, YU-HSUN CHEN
  • Patent number: 11545385
    Abstract: A carrier structure having a strengthening layer is provided. The strengthening layer comprises 5 to 30% by weight polysiloxane, 1 to 20% by weight silicon dioxide, and 60 to 85% by weight polyethylene terephthalate (PET) film. The carrier structure is used in a semiconductor packaging process for improving the process reliability.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 3, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Tse-Yuan Lin, Chun-Ming Laio, Yu-Chih Cheng
  • Patent number: 11542347
    Abstract: This invention relates to a one-step process for making a polymer composite suspension for coating plastic films characterized in that a first polymer is synthesized in-situ optionally in the presence of other polymers and in the presence of clay. Preferably the polymer composite suspension comprises a) 1.0 to 11.0 wt % of clay or silane modified clay, b) 0.1 to 10.0 wt % of poly (acrylic acid), which is a copolymer of acrylic acid (AA) with at least one other monomer selected from 2-ethylhexyl acrylate (EHA), ?-carboxyethyl acrylate (?-CEA), methacrylamidoethyl ethylene urea (WAM II) and ethoxylated behenyl methacrylate (?-FM), c) 1.0 to 15.0 wt % of other polymers, preferably poly (vinyl alcohol) and d) 70 to 97 wt % of water or mixture of water with 2-propanol. The coating films made from the suspensions show good barrier capabilities against water vapor and oxygen can be used to make barrier layers on or within plastic films for packaging applications.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: January 3, 2023
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Xu Li, Yu Yuan Chieng, Siew Yee Wong, Xikui Zhang
  • Patent number: 11545557
    Abstract: A semiconductor device includes substrate having a fin structure thereon, a gate structure overlying the fin structure, a polymer block at a corner between the gate structure and the fin structure, and a source/drain region on the fin structure. The polymer block includes a nitridation layer in proximity to a sidewall of the gate structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Chang, Chia-Ming Kuo, Po-Jen Chuang, Fu-Jung Chuang, Shao-Wei Wang, Yu-Ren Wang, Chia-Yuan Chang
  • Publication number: 20220415737
    Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Wu, Ting Hao Kuo, Kuo-Lung Pan, Po-Yuan Teng, Yu-Chia Lai, Shu-Rong Chun, Mao-Yen Chang, Wei-Kang Hsieh, Pavithra Sriram, Hao-Yi Tsai, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220415398
    Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Deepanshu Dutta
  • Publication number: 20220410054
    Abstract: A smoke and dust treatment apparatus for welding, said apparatus comprising a polishing and dust extraction module and a smoke and dust purification module. The polishing and dust extraction module comprises a double-layer dust extraction cover (3), a protective cover (2), an industrial brush (4), a first air guide portion, a second air guide portion (24) and a drive motor (22), the drive motor (22) driving the industrial brush (4) to rotate at high speed to perform polishing. During welding and polishing, a mechanical arm (6) drives the double-layer dust extraction cover (3), and a suction hole (20) of the double-layer dust extraction cover (3) and a suction guide hole (19) on the industrial brush (4) simultaneously take in toxic gas and debris such as iron filings.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 29, 2022
    Inventors: Liang HUA, Jiahao ZHAO, Junguo ZHU, Binhui PEI, Chang YUAN, Liangliang SHANG, Laiwu LUO, Yu TANG, Yuze CHENG, Delin HU, Benteng GUO, Jin GU
  • Publication number: 20220416836
    Abstract: A wireless communication system having a dual-band coexistence architecture is provided, and the system includes a processing circuit, a first transceiver, a first front-end module, a first switch circuit, a first filter, a second filter, a second switch circuit, a first antenna, a second transceiver, a second front-end module, a third switch circuit, a third filter, a fourth filter, a fourth switch circuit and a second antenna. The first filter and the second filter use a combination of a wideband filter and a narrowband filter, and the fourth filter and the third filter also use a combination of a wideband filter and a narrowband filter, so as to achieve the dual-band coexistence architecture.
    Type: Application
    Filed: October 25, 2021
    Publication date: December 29, 2022
    Inventors: CHEN-MAO RAO, LI-YUAN CHANG, YU-FANG CHANG
  • Publication number: 20220415399
    Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-yuan Tseng
  • Publication number: 20220404193
    Abstract: Reducing an average give-away rate of a weighing device by determining a weight of a product of a weighing device that includes an article, determining one or more conditions of an environment of the weighing device, determining a state of the environment of the weighing device, wherein the state relates to an average give-away rate of the environment of the weighing device, determining a reward value for the state of the environment of the weighing device, wherein the reward value is based at least in part on the weight of the product, and generating a set of parameters for the weighing device based at least in part on the environment, the state, and the reward.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Deng Xin Luo, Xiang Yu Yang, Yong Wang, Ye Wang, Zhong Fang Yuan, Yu Pan
  • Publication number: 20220405524
    Abstract: A method, computer system, and a computer program product for optical character recognition training are provided. A text image and plain text labels for the text image may be received. The text image may include words. The plain text labels may include machine-encoded text corresponding to the words. Semantic feature vectors for the words, respectively, may be generated based on the plain text label. The text image, the plain text labels, and the semantic feature vectors may be input together into a machine learning model to train the machine learning model for optical character recognition. The plain text labels and the semantic feature vectors may be constraints for the training.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Zhong Fang Yuan, Tong Liu, Jing Wen Xu, Xiang Yu Yang, Yu Pan, Wei NB Wu
  • Patent number: 11532550
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes forming a trench in a dielectric layer on a semiconductor substrate; forming a bottom metal feature of a first metal in a lower portion of the trench by a selective deposition; depositing a barrier layer in an upper portion of the trench, the barrier layer directly contacting both a top surface of the bottom metal feature and sidewalls of the dielectric layer; and forming a top metal feature of a second metal on the barrier layer, filling in the upper portion of the trench, wherein the second metal is different from the first metal in composition.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yuan Chen, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11532717
    Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao