Patents by Inventor Yuan Chen

Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261434
    Abstract: An integrated circuit includes a feedthrough via structure includes a dummy transistor with a dummy gate metal. The dummy transistor is positioned between a first transistor and a second transistor. The dummy gate metal is a different material than the gate metal of the first and second transistors. The feedthrough via structure and electrically connects a backside metal line with a front side metal line. The first and second transistors are positioned between the front side of backside metal lines.
    Type: Application
    Filed: July 19, 2024
    Publication date: August 14, 2025
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Chih-Hao WANG
  • Publication number: 20250259890
    Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.
    Type: Application
    Filed: April 1, 2025
    Publication date: August 14, 2025
    Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20250259911
    Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first conductive feature disposed between two substrate portions, a second conductive feature disposed over the first conductive feature, a third conductive feature disposed over the first conductive feature, and a fourth conductive feature disposed over the first conductive feature. The fourth conductive feature includes a top portion disposed over the second and third conductive features and a bottom portion disposed between the second and third conductive features, and the first, second, third, and fourth conductive features are electrically connected.
    Type: Application
    Filed: May 29, 2024
    Publication date: August 14, 2025
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Chih-Hao WANG
  • Patent number: 12386222
    Abstract: A display device includes a backlight module and a display module. The backlight module includes a plurality of light emitting units, a base plate and at least one controller. The light emitting units are disposed on a first surface of the base plate, the controller is disposed on a second surface of the base plate, the second surface is opposite to the first surface, and at least one of the light emitting units is electrically connected to the controller. The display module is disposed on the first surface, and the light emitting units are disposed between the display module and the base plate. The backlight module includes a covering layer, an optical film, and a plurality of pins, the covering layer is disposed on the first surface of the base plate, and the pins are disposed between the covering layer and the optical film.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: August 12, 2025
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai, Jia-Yuan Chen
  • Patent number: 12389710
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: August 12, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Yun Yang, Chun-Yuan Chen, Ching I Li
  • Publication number: 20250253242
    Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.
    Type: Application
    Filed: February 17, 2025
    Publication date: August 7, 2025
    Inventors: Yu-Xuan Huang, Wei-Cheng Lin, Yi-Hsun Chiu, Chun-Yuan Chen, Wei-An Lai, Yi-Bo Liao, Hou-Yu Chen, Ching-Wei Tsai, Ming Chian Tsai, Huan-Chieh Su, Jiann-Tyng Tzeng, Kuan-Lun Cheng
  • Publication number: 20250254914
    Abstract: A semiconductor device comprises semiconductor layers extending over a substrate, a gate structure, gate spacers, epitaxial source/drain structures, a conductive contact and a lower dielectric plug. The gate structure wraps around the semiconductor layers. The gate spacers are on opposite sidewalls of the gate structure. The epitaxial source/drain structures are on opposite sides of the metal gate structure. The conductive contact is over a first one of the epitaxial source/drain structures. The lower dielectric plug is over a second one of epitaxial source/drain structures, wherein from a cross-sectional view, the gate spacers are between the lower dielectric plug and the conductive contact, wherein from a plan view, the lower dielectric plug and the conductive contact have a same pattern.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 7, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Chien WU, Chun-Yuan CHEN, Huan-Chieh SU, Chih-Hao WANG
  • Publication number: 20250249670
    Abstract: The present disclosure provides a synthetic leather including a base layer, a first polyolefin layer and a second polyolefin layer. The first polyolefin layer is disposed on the base layer, and a Shore A hardness thereof is about 40A to about 70A. The second polyolefin layer is disposed on the first polyolefin layer, and a Shore A hardness thereof is about 75 to about 98.
    Type: Application
    Filed: January 16, 2025
    Publication date: August 7, 2025
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, CHI-CHIN CHIANG, LI-YUAN CHEN, ZI HAO HSU
  • Patent number: 12382709
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
    Type: Grant
    Filed: January 5, 2024
    Date of Patent: August 5, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Chun-Yuan Chen, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20250244152
    Abstract: An automotive sensor includes a body and a connecting member. The body forms a workspace. The connecting member is inserted into the body and includes a primary end, and the primary end is arranged in the workspace and includes a holding portion. The automation of the assembly process can be realized, and then the effect of improving assembly efficiency and reducing labor cost can be achieved.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 31, 2025
    Inventors: HUNG-SHUAN LIN, CHIH-EN WANG, TZU-CHIEH LIN, HSIN-YUAN CHEN, PENG-YUAN TAI
  • Publication number: 20250246544
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Application
    Filed: April 16, 2025
    Publication date: July 31, 2025
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Publication number: 20250248170
    Abstract: A manufacturing method of a display device includes the following steps. A substrate is provided. The substrate has a pixel region, and a driving circuit is disposed on the pixel region. Light emitting elements are placed in a light emitting element mounting region of the pixel region. A force of an electric field between a first alignment electrode and a second alignment electrode is used to substantially align the light emitting elements in one direction and fix the light emitting elements in the light emitting element mounting region of the pixel region. An insulation layer is formed on the aligned light emitting elements to further fix the aligned light emitting elements in the light emitting element mounting region of the pixel region. The aligned light emitting elements are electrically connected to the driving circuit. The substrate carrying the aligned light emitting elements is cut into multiple sub-substrates.
    Type: Application
    Filed: April 18, 2025
    Publication date: July 31, 2025
    Applicant: Innolux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee
  • Patent number: 12373151
    Abstract: A display device, a display system, and a display and control method are provided. The display device includes a display module, a first multimedia interface, a second multimedia interface, and a controller. The controller receives first picture data of a first picture of a first electronic device via the first multimedia interface, and receives second picture data of a second picture of a second electronic device via the second multimedia interface. The controller determines a content of a display picture displayed by the display module according to the first picture data and the second picture data, and the controller determines whether an input device is used to control the first electronic device or the second electronic device according to a mouse position in the display picture.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: July 29, 2025
    Assignee: Wistron Corporation
    Inventor: Feng Yuan Chen
  • Patent number: 12376356
    Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.
    Type: Grant
    Filed: February 28, 2024
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Chih-Hao Wang
  • Publication number: 20250241099
    Abstract: A method for manufacturing a display device is provided. The method includes providing a driving module, disposing at least two light emitting units on the driving module and electrically connected to the driving module, providing a light conversion module, and disposing the light conversion module on the driving module. The light conversion module includes a first light conversion layer, a second light conversion layer, and a light blocking pattern disposed at a side of the first light conversion layer and the second light conversion layer, and an overlapping region of the first light conversion layer and the second light conversion layer is overlapped with the light blocking pattern in a top view direction.
    Type: Application
    Filed: March 6, 2025
    Publication date: July 24, 2025
    Applicant: InnoLux Corporation
    Inventors: Jia-Yuan CHEN, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20250241005
    Abstract: Using a same hardmask layer during formation of some isolation structures (e.g., shallower shallow trench isolation structures) and during formation of additional isolation structures (e.g., shallow trench isolation structures) results in the isolation structures being approximately level with a horizontal surface of a substrate in which the isolation structures are formed. That is, a step height of the isolation structures is reduced. Therefore, heights of portions of gates that extend over the isolation structures are increased. The increased heights of the gates result in increased landing areas for contacts, which helps prevent current leakage and thus improves performance of electronic devices that include the isolation structures.
    Type: Application
    Filed: January 19, 2024
    Publication date: July 24, 2025
    Inventors: Chung-Huai CHANG, Wen-Hao CHEN, Chien-Yuan CHEN, Hsueh-Liang CHOU
  • Publication number: 20250235881
    Abstract: A sprayer head has a main body and an output head, wherein the main body comprises an output column with a water channel having a plurality of output aperture channels passing through the output column; the output column comprises a first threaded section and a control lever at a closed front end, and the control lever is jacketed with a first sealing ring. The output head has a connecting ring, a conic sleeve and a control member, the connecting ring being made of plastic and having a second threaded section for engaging with the first threaded section, and two opposing latches on an outer periphery; the conic sleeve is made of metal and has two opposing L-shaped rotatable slots on an outer periphery.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 24, 2025
    Inventor: Chin-Yuan Chen
  • Publication number: 20250236100
    Abstract: A polymer structure and applications thereof are provided. The polymer structure includes a substrate and a light shielding layer covering at least a portion of the surface of the substrate, wherein the substrate includes a first polymer, the light shielding layer comprises a second polymer which includes a structural unit derived from a first ultraviolet absorber, the light shielding layer has a thickness of 1 ?m to 200 ?m, and the first ultraviolet absorber is a polyfunctional reactive ultraviolet absorber.
    Type: Application
    Filed: November 15, 2022
    Publication date: July 24, 2025
    Inventors: Ching-Hao CHENG, Huang-Min WU, Wei-Chun CHANG, Yi-Shuo HUANG, Chi-Feng WU, De-Shun LUO, Si-Yuan CHEN, Yen-Hei CHIANG
  • Patent number: 12369406
    Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsi-Yu Kuo, Tsung-Yuan Chen, Yu-Lin Chu, Chih-Wei Hsu
  • Publication number: 20250233018
    Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 17, 2025
    Inventors: Chun-Yuan Chen, Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin