Patents by Inventor Yuan Chen

Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240251568
    Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 25, 2024
    Inventors: Tai-Yen Peng, Tsung-Hsien Chang, Yu-Shu Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Chung-Te Lin
  • Publication number: 20240250134
    Abstract: A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.
    Type: Application
    Filed: May 8, 2023
    Publication date: July 25, 2024
    Inventors: Chun-Yuan Chen, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Kuo-Nan Yang
  • Publication number: 20240250143
    Abstract: Conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Application
    Filed: February 28, 2024
    Publication date: July 25, 2024
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Publication number: 20240249494
    Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.
    Type: Application
    Filed: September 4, 2023
    Publication date: July 25, 2024
    Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
  • Publication number: 20240248280
    Abstract: A driving mechanism for moving an optical element is provided. The driving mechanism includes a fixed part, a movable part, a driving assembly, and a first guiding member. The optical element is disposed on the movable part. The driving assembly drives the movable part to move relative to the fixed par. The first guiding member is disposed between the fixed part and the movable part. The movable part is guided by the first guiding member when moving relative to the fixed part.
    Type: Application
    Filed: January 19, 2024
    Publication date: July 25, 2024
    Inventors: Po-Xiang ZHUANG, Chao-Yuan CHANG, Wei-Jhe SHEN, Sin-Jhong SONG, Kun-Shih LIN, Yi-Ho CHEN, Chao-Chang HU
  • Publication number: 20240245037
    Abstract: A multi-use monitoring system is disclosed, which comprises an electronic device, multiple sensor devices, multiple cameras, at least one wireless interface, and a remote electronic device. According to the present invention, the sensor devices are adopted for detecting multiple environmental parameters such as gas level, humidity and temperature, and the multiple cameras are controlled to acquire images from the poultry bred in a breeding environment. Therefore, after receiving the images and the environmental parameters from the electronic device, the remote electronic device can extract at least one poultry characteristic from the images, and then correlate the environmental parameters to the poultry characteristic(s). As a result, the remote electronic device can subsequently calculate an evaluation score according to the growth and/or health state of the poultry, such that the breeder can plan how to distribute the breeding resources for the poultry.
    Type: Application
    Filed: January 22, 2024
    Publication date: July 25, 2024
    Applicant: CALYX, INC.
    Inventors: Po-Jui CHIU, Benson FAN, Ming-Yuan TSAI, I-Ting CHEN, Chia-Cheng LIAO, Shin-Kai MA, Tsung-Lin LU, Chan-Hsin YEH, To-An TING, Ting-Shuo CHANG
  • Publication number: 20240249969
    Abstract: A wafer carrier with a bottom for connecting to a shaft includes a disc body and at least one heat insulator. The disc body has an accommodating groove for accommodating a wafer, and the disc body has a first surface and a second surface opposing each other. A groove bottom of the accommodating groove has the first surface. The at least one heat insulator is disposed on either the first surface or the second surface. When the wafer is accommodated in the accommodating groove, the at least one heat insulator is positioned between the wafer and the shaft.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 25, 2024
    Applicant: GLOBALWAFERS CO., LTD.
    Inventors: CHIH-YUAN CHUANG, JUI-PIN CHEN, JIA-ZHE LIU
  • Patent number: 12046286
    Abstract: A semiconductor circuit and an operating method for the same are provided. The semiconductor circuit includes strings. The strings include a first string and a second string. The first string includes a first device unit and a second device unit in series. The first string has a weight signal W1. The first device unit has an input signal A. The second device unit has an input signal B. The second string includes a third device unit and a fourth device unit in series. The second string has a weight signal W2. The third device unit has an input signal ?. The fourth device unit has an input signal B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: July 23, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yun-Yuan Wang, Wei-Chen Chen, Dai-Ying Lee, Ming-Hsiu Lee
  • Patent number: 12046516
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Cheng-Chi Chuang, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 12046550
    Abstract: Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Paul Yang, Tsun-Kai Tsao, Sheng-Chau Chen, Sheng-Chan Li, Cheng-Yuan Tsai
  • Publication number: 20240243046
    Abstract: A flip chip ball grid array package includes a package substrate and a flip chip device mounted on a top surface of the package substrate. The flip chip device includes a semiconductor integrated circuit die; an epoxy molding compound encapsulating vertical sidewalls of the semiconductor integrated circuit die; a re-distribution layer structure disposed on an active surface of the semiconductor integrated circuit die and on a lower surface of the epoxy molding compound; a sintered nanosilver layer disposed on a passive rear surface of the semiconductor integrated circuit die and on an upper surface of the epoxy molding compound; and a stiffener ring mounted around the flip chip device on the package substrate.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 18, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chun-Yin Lin, Tai-Yu Chen, Li-Song Lin, Chi-Yuan Chen
  • Publication number: 20240240821
    Abstract: A chiller system provides cooling for a semiconductor fabrication facility. The chiller system includes a control system. The control system utilizes one or more analysis models trained with a machine learning process to intelligently assist in reducing the power consumption and enhancing the efficiency of the chiller system.
    Type: Application
    Filed: January 12, 2023
    Publication date: July 18, 2024
    Inventors: Chih-Neng Chang, Tzu-Wei Chien, Chien-Wei Chen, Fu-Chun Chang, Kun-Hsien Tsai, Kai-Yuan Cheng
  • Publication number: 20240244534
    Abstract: Examples pertaining to repeater gain control for device collaboration in distributed MIMO systems are described. An apparatus (e.g., a repeater) may determine a first compensation value for a first path loss on a first link between the apparatus and a UE, and determine a second compensation value for a second path loss on a second link between the apparatus and a network node of a wireless network. The apparatus may also determine a repeater gain for uplink power control according to the first compensation value and the second compensation value. The apparatus may further forward a radio signal from the UE to the network node according to the repeater gain.
    Type: Application
    Filed: December 20, 2023
    Publication date: July 18, 2024
    Inventors: Kuan-Yuan Chen, Lung-Sheng Tsai
  • Publication number: 20240243108
    Abstract: An electronic device is provided. The electronic device includes a substrate, a plurality of light-emitting elements, and a protective layer. The substrate includes a connecting element. The plurality of light-emitting elements is disposed on the substrate. The protective layer is disposed on the substrate and includes an opaque layer and a transparent layer. The opaque layer has a plurality of openings. At least a portion of the transparent layer is disposed in the openings and covers the respective light-emitting elements. The protective layer surrounds the connecting element.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 18, 2024
    Inventors: Jui-Jen YUEH, Kuan-Feng LEE, Jia-Yuan CHEN, Cheng-Chi WANG
  • Publication number: 20240239059
    Abstract: A molding method of a support rod that first passing a plurality of long fibers through a resin bath for impregnating with resin, then passing the plurality of long fibers impregnated with resin through a bundling hole of a position-constrained vertical plate on a machine to preliminarily form a bundle end; providing a coating layer on the machine, one end of the coating layer obliquely passes through a guiding portion on the position-constrained vertical plate to downwardly contact the bundle end; then placing the one end of the coating layer and the bundle end into a mold cavity of a mold at the same time to form a long rod body; and then cutting the long rod body into multi-segment support rods through a cutting process.
    Type: Application
    Filed: May 17, 2023
    Publication date: July 18, 2024
    Inventors: Che-Yuan Liu, Chang-Hsing Lee, Ming-Chuan Liu, Zhao-Xu Lai, Pen-Chien Yu, Shu-Fen Wang, Chia-Chang Hsu, Ren-Wei Tsai, Zong-You Chen, Da-Chun Chien
  • Publication number: 20240244916
    Abstract: An electronic device emitting an output light includes an optical layer. The electronic device emits the output light under an operation of a highest brightness. The output light has an output spectrum, an intensity integral of the output spectrum from 380 nm to 489 nm is defined as a first intensity integral, and an intensity integral of the output spectrum from 490 nm to 780 nm is defined as a second intensity integral. A ratio of the first intensity integral over the second intensity integral is defined as a first ratio, and the first ratio is greater than 0% and less than or equal to 7.5%.
    Type: Application
    Filed: January 23, 2024
    Publication date: July 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Jui-Jen Yueh, Kuan-Feng Lee, Jia-Yuan Chen
  • Publication number: 20240243168
    Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: CHE-YUAN CHANG, HUI-ZHONG ZHUANG, CHIH-LIANG CHEN
  • Patent number: 12037627
    Abstract: A Lactobacillus paracasei and uses thereof. The Lactobacillus paracasei has a deposit number of CGMCC No. 14813. The Lactobacillus paracasei can be used for increasing the amount of an organic acid in a raw material. The Lactobacillus paracasei can be used for fermenting the raw material, where the raw material can be selected from at least one of fruits, which can increase the content of the organic acid in a fermented product.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: July 16, 2024
    Assignee: CHINA NATIONAL RESEARCH INSTITUTE OF FOOD & FERMENTATION INDUSTRIES CO., LTD.
    Inventors: Muyi Cai, Ruizeng Gu, Jun Lu, Kong Ling, Lu Lu, Ming Zhou, Xinyue Cui, Xingchang Pan, Zhe Dong, Yong Ma, Yaguang Xu, Yongqing Ma, Liang Chen, Ying Wei, Haixin Zhang, Yan Liu, Kelu Cao, Jing Wang, Guoming Li, Yuchen Wang, Yuqing Wang, Yuan Bi, Xiuyuan Qin
  • Patent number: 12040381
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
  • Patent number: D1036422
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: July 23, 2024
    Inventor: Yuan Chen