Patents by Inventor Yuan Chen

Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10814314
    Abstract: The present invention relates to a catalyst for aminating a polyether polyol and preparation method thereof and a method of preparing a polyetheramine using the catalyst. The catalyst has active components and a carrier. The active components are Ni, Cu, and Pd. The method of preparing the catalyst comprises the following steps: using a metal solution or a metal melt impregnated carrier, obtaining a catalyst precursor; and drying and calcinating the obtained catalyst precursor, so as to obtain a catalyst. By introducing the active component Pd in the catalyst, the present invention clearly improves selectivity of an amination catalyst with respect to a preaminated product, and increases raw material conversion rate.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: October 27, 2020
    Assignee: Wanhua Chemical Group Co., Ltd.
    Inventors: Congying Zhang, Shujie Ren, Xin Li, Zhenguo Liu, Xiaolong Wang, Ningning Wang, Hao Chen, Yuan Li, Xueli Yu, Jinhong Song
  • Patent number: 10820387
    Abstract: An embodiment of the disclosure provides a light source apparatus including a light-emitting module and a control unit. The light-emitting module is configured to provide a light. The control unit is configured to change proportion of a first sub-light and a second sub-light to form the light so that a circadian action factor (CAF) and a correlated color temperature (CCT) of the light varies along a CAF vs. CCT locus of the light different from a CAF vs. CCT locus of sunlight. A CAF vs. CCT coordinate of one of the first sub-light and the second sub-light is below the CAF vs. CCT locus of sunlight, and a CAF vs. CCT coordinate of the other one of the first sub-light and the second sub-light is above the CAF vs. CCT locus of sunlight. A display apparatus is also provided.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: October 27, 2020
    Assignees: Avertronics INC, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bing-Yuan Lai, Chi-I Lai, Jun-Yu Wu, Tzung-Te Chen, Shih-Yi Wen, Chia-Fen Hsieh
  • Patent number: 10813906
    Abstract: Disclosed herein is a method for treating infection by an enteropathogen and/or enhancing growth performance, which includes administering to a subject in need thereof a composition containing a ferrous amino acid chelate. Also disclosed herein is an animal feed containing the ferrous amino acid chelate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 27, 2020
    Assignee: PROFEAT BIOTECHNOLOGY CO., LTD.
    Inventors: Tsun-Yuan Lin, Mu-Kuei Chen, Kai-Ting Wang, Hsun-Jin Jan
  • Patent number: 10817118
    Abstract: A display touch device includes a touch panel disposed on one side of a display panel and third patterned electrodes disposed on a supporting substrate. The touch panel includes a transparent substrate; first and second patterned electrodes respectively disposed on the transparent substrate in first and second direction. Mutual capacitors are formed between the first and second patterned electrodes, and the first and second patterned electrodes form a touch sensor structure. The first patterned electrodes or the second pattern electrodes partially overlap with the third patterned electrodes in a third direction to form a pressure sensor structure. The third direction is a stacking direction of the display panel and the touch panel. The touch sensor structure performs touch sensing in a first period of a frame and performs pressure sensing in a second period of the frame. The first period does not overlap the second period.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 27, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Po-Yang Chen, Hsing-Yuan Hsu, Kuei-Sheng Chang, I-An Yao
  • Patent number: 10816593
    Abstract: A testing system is suitable for receiving at least one testing item of multiple device under tests (DUTs). The testing system comprises a plurality of testing devices and an arrangement unit. The arrangement unit is coupled to the testing devices. The arrangement unit generates at least one testing instruction according to the at least one testing item and detects an idle state corresponding to the at least one testing instruction, and transmits the at least one testing instruction to the testing device in the idle state, so as to trigger the testing device in the idle state to test the corresponding DUT according to the at least one testing instruction and generate a testing result.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 27, 2020
    Assignee: PEGATRON CORPORATION
    Inventors: Chih-Ho Chen, Wen-Pin Li, Guo-Yuan Tseng, Yu-Ting Chen
  • Publication number: 20200335288
    Abstract: A waterproof button module includes a pressing element, a circuit board, an adhesive layer, and an elastic layer sequentially stacked. The adhesive layer is attached to the circuit board and the elastic layer. The adhesive layer includes a first opening, and the elastic layer includes a second opening. The first opening is aligned with the second opening and exposes a part of the rear surface of the circuit board. The adhesive layer has an annular zone adjacent to and surrounding the first opening. The annular zone directly contacts the circuit board. The waterproof button module further includes an electric-connection assembly and a switch. The electric-connection assembly is electrically connected to the circuit board, and passes through the first opening and the second opening. The switch is electrically connected to the circuit board, and has a button. In addition, an electronic device including the waterproof button module is disclosed.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 22, 2020
    Inventors: XIAO LI, CHIH-YUAN CHEN, SHUN-LONG LEE
  • Publication number: 20200335353
    Abstract: A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends along sidewalls of the bottom electrode, the switching dielectric, and the top electrode and an upper surface of a lower dielectric layer. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The the sidewall spacer layer separates the lower etch stop layer from the lower dielectric layer.
    Type: Application
    Filed: June 30, 2020
    Publication date: October 22, 2020
    Inventors: Sheng-Chau Chen, Cheng-Tai Hsiao, Cheng-Yuan Tsai, Hsun-Chung Kuang, Yao-Wen Chang
  • Publication number: 20200334338
    Abstract: A wafer characteristic prediction method and an electronic device are provided. The method includes: receiving a process parameter of a wafer during a mass production; inputting the process parameter to a prediction model to obtain a wafer characteristic of the wafer being mass produced; and outputting the wafer characteristic.
    Type: Application
    Filed: July 22, 2019
    Publication date: October 22, 2020
    Applicant: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Yuan-Hung Liao, Chih-Chen Liu
  • Publication number: 20200334191
    Abstract: A method for processing a multi-media signal and an associated multi-media device are provided. The method includes: receiving a first audio signal within the multi-media signal from a display device through a first transmission interface of a multi-media device; converting the first audio signal into a second audio signal applicable to a second transmission interface of the multi-media device; and outputting the second audio signal to an audio device through the second transmission interface for playback.
    Type: Application
    Filed: January 16, 2020
    Publication date: October 22, 2020
    Inventors: Chao-Min Lai, Chia-Hao Wu, Yan-Jyun Chen, Guo-Yuan Luo
  • Publication number: 20200336004
    Abstract: An electronic device includes a backup power supply unit, a first power management unit, a switch, a voltage detection unit, a processor and an electronic module. The first power management unit is coupled to the backup power supply unit and an external power supply unit. The switch is coupled to the first power management unit. The voltage detection unit is coupled to the external power supply unit and the switch. The processor is coupled to the voltage detection unit. The electronic module is coupled to the switch and the processor. When a voltage level of the external power supply unit is lower than a first predetermined level, the voltage detection unit outputs a detection signal. The switch is controlled by the detection signal to open to stop supplying power to the electronic module. The processor is controlled by the detection signal to execute a shutdown process.
    Type: Application
    Filed: July 24, 2019
    Publication date: October 22, 2020
    Inventors: Wen-Yuan Chen, Ren-Yuan Cheng, Chen-Kang Wang
  • Publication number: 20200333558
    Abstract: An optical member driving mechanism is provided, including a movable portion, a fixed portion, and a driving assembly. The movable portion is connected to an optical member. The movable portion is movable relative to the fixed portion. The driving assembly is configured to drive the movable portion to move relative to the fixed portion.
    Type: Application
    Filed: January 17, 2020
    Publication date: October 22, 2020
    Inventors: Fu-Yuan WU, Sheng-Zong CHEN
  • Publication number: 20200335507
    Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
  • Patent number: 10811420
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 20, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Szu-Han Chen, Hsu Chiang, Ching-Yuan Kuo
  • Patent number: 10812057
    Abstract: A time detection circuit and a time detection method are provided. The time detection circuit includes an input signal processor and a time signal amplifier. The input signal processor receives a first input signal and a second input signal, calculates a time difference value between the first input signal and the second input signal, adjusts the time difference value by comparing the time difference value with a set reference value, and provides the adjusted time difference value. The time signal amplifier receives the adjusted time difference value, and amplifies the adjusted time difference value to generate an amplified time signal. The time signal amplifier operates in a linear operation region between a first time value and a second time value, and the set reference value is set according to the first time value and the second time value.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Pei-Yuan Chou, Jinn-Shyan Wang, Chuen-Shiu Chen
  • Patent number: 10811465
    Abstract: Provided are a display panel and a display device. The display panel includes a display region having a first steplike edge. The display region is provided with a plurality of sub-pixel groups. Each sub-pixel group includes a first sub-pixel unit, a second sub-pixel unit and a third sub-pixel unit. The first sub-pixel unit, the second sub-pixel unit and the third sub-pixel unit have different luminous colors. Along a connecting line of step apex angles of the first steplike edge, the display region is provided with a plurality of first sub-pixel groups and a plurality of second sub-pixel groups. The first sub-pixel unit in each first sub-pixel group is disposed at a step apex angle of the first steplike edge, and the second sub-pixel unit in each second sub-pixel group is disposed at the step apex angle of the first steplike edge.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 20, 2020
    Assignee: Shanghai Tianma AM-OLED Co., Ltd.
    Inventors: Yuan Li, Xian Chen, Lijing Han, Kaihong Huang
  • Patent number: 10811369
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Ming-Da Cheng, Wen-Hsiung Lu
  • Publication number: 20200326021
    Abstract: A faucet connector has a first tubular body is provided with an assembly aperture, and the first tubular body is convexly disposed on the inner wall of the assembly aperture. A second tubular body is formed with an inserting portion at one end, and the inserting portion is penetrated by an inner threaded aperture. The second tubular body is disposed at the assembly aperture. A third tubular body is formed with a ring at one end, the third tubular body has a threaded portion at the other end, and the third tubular body is placed at the first tubular body inside the assembly aperture of the tubular body. The threaded portion of the third tubular body is locked to the inner threaded hole of the second tubular body, so that the ring fits the inserting portion at both ends of the lip.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 15, 2020
    Inventor: Chin-Yuan Chen
  • Publication number: 20200328142
    Abstract: A package stack structure and a method for fabricating the same are provided. An electronic component is disposed on the topmost one of a plurality of organic material substrates, and no chip is disposed on the remaining organic material substrates. A predefined layer number of circuit layers are disposed in the organic material substrates, and distributes the thermal stress via the organic material substrates. Therefore, the bottommost one of the organic material substrates will not be separated from a circuit board due to CTE mismatch. Also a carrier component is provided.
    Type: Application
    Filed: August 12, 2019
    Publication date: October 15, 2020
    Inventors: Don-Son Jiang, Nai-Hao Kao, Chih-Sheng Lin, Szu-Hsien Chen, Chih-Yuan Shih, Chia-Cheng Chen, Yu-Cheng Pai, Hsuan-Hao Mi
  • Publication number: 20200327274
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN