Patents by Inventor Yuan Chen

Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250203931
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures and a first epitaxial structure and a second epitaxial structure sandwiching one or more of the stack of semiconductor nanostructures. The semiconductor device structure also includes a backside conductive contact electrically connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the stack of semiconductor nanostructures. The semiconductor device structure further includes an insulating spacer beside a second portion of the backside conductive contact extending towards the second epitaxial structure.
    Type: Application
    Filed: March 4, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20250187033
    Abstract: A garden hose nozzle includes a hose nozzle body, at least one sprinkler head, and a water stop ring. The hose nozzle body includes a barrel part, one end of the barrel part is formed with a port, an inner wall of the barrel part is provided with two stoppers, two entrance channels, and two swivel slots. The stopper is formed a limiting block protruding from an inner end close to one side of the entrance channel, and the limiting block is provided a first inclined guide surface. A sleeve pipe extends from one end of the sprinkler head, an outer wall of the sleeve pipe is provided with two projecting ribs, and the projecting rib is formed a second inclined guide surface.
    Type: Application
    Filed: December 7, 2023
    Publication date: June 12, 2025
    Applicant: SHIN TAI SPURT WATER OF THE GARDEN TOOLS CO., LTD.
    Inventor: Chin-Yuan Chen
  • Publication number: 20250188601
    Abstract: Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).
    Type: Application
    Filed: February 18, 2025
    Publication date: June 12, 2025
    Inventors: Pin-Wen CHEN, Yuan-Chen HSU, Ken-Yu CHANG
  • Publication number: 20250186562
    Abstract: The disclosure is directed to peptidomimetic compounds, or pharmaceutically acceptable salts thereof, pharmaceutical compositions comprising such peptidomimetic compounds, and methods for degrading target substrate proteins using such compounds.
    Type: Application
    Filed: March 8, 2023
    Publication date: June 12, 2025
    Inventors: Yuan Chen, Nicole Thomas, Abdelfattah Faouzi
  • Publication number: 20250192117
    Abstract: An electronic assembly is provided. The electronic assembly includes a first circuit structure including a transistor, a through via and a conductive structure, a plurality of electronic elements disposed on the first circuit structure, a first pad disposed between the first circuit structure and one of the plurality of electronic elements, a second circuit structure disposed on the first circuit structure, and a second pad disposed between the second circuit structure and one of the plurality of electronic elements. At least a portion of the conductive structure is disposed in the through via. The conductive structure is electrically connected to the first pad and the transistor.
    Type: Application
    Filed: February 14, 2025
    Publication date: June 12, 2025
    Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE, Yuan-Lin WU
  • Publication number: 20250185348
    Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain epitaxial features; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside; and a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.
    Type: Application
    Filed: February 10, 2025
    Publication date: June 5, 2025
    Inventors: Chun-Yuan Chen, Yu-Ming Lin, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su
  • Publication number: 20250185353
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second dummy epitaxial layers disposed in first and second base structures, first and second active epitaxial layers disposed on the first and second dummy epitaxial layers, a first active nanostructured layer disposed adjacent to and in contact with the first active epitaxial layer, a second active nanostructured layer disposed adjacent to and in contact with the second active epitaxial layer, a dummy nanostructured layer disposed adjacent to and in contact with the second dummy epitaxial layer, a first gate structure surrounding the first active nanostructured layer, and a second gate structure surrounding the second active nanostructured layer and the dummy nanostructured layer.
    Type: Application
    Filed: June 27, 2024
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Sheng-Tsung Wang, Chun-Yuan Chen, Huan-Chieh Su, Lo-Heng Chang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Patent number: 12323753
    Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a protrusion extending into the air gap.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: June 3, 2025
    Assignee: FORTEMEDIA, INC.
    Inventors: Chih-Yuan Chen, Feng-Chia Hsu, Chun-Kai Mao, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
  • Publication number: 20250170295
    Abstract: A contact lens includes a composition of the contact lens. The composition of the contact lens includes a humectant. The humectant includes a glucan, and the glucan in the composition of the contact lens includes an 1-3/1-6-glucan. The contact lens product includes the contact lens and the buffer solution, and the contact lens is immersed in the buffer solution.
    Type: Application
    Filed: October 18, 2024
    Publication date: May 29, 2025
    Inventors: Wei-Yuan CHEN, Yi Shyang HUANG, Yu-Yi SHIH, Wei-Chun CHEN, Yu Yin NI, Yu Jie HONG, Chun-Hung TENG
  • Publication number: 20250174533
    Abstract: A semiconductor package structure includes a package substrate. The package substrate includes a first core structure, a plurality of first dielectric layers, a plurality of first metal layers, a plurality of second dielectric layers, and a plurality of second metal layers. The first core structure has a first surface and a second surface opposite the first surface. The first dielectric layers and the first metal layers are alternatingly stacked on the first surface of the first core structure. The second dielectric layers and the second metal layers are alternatingly stacked on the second surface of the first core structure. A number of second dielectric layers is less than a number of first dielectric layers.
    Type: Application
    Filed: June 7, 2024
    Publication date: May 29, 2025
    Inventors: Yih-Ting SHEN, Tai-Yu CHEN, Ping-Yeh LIN, Yu-Jin LI, Chun-Yi CHANG, Chi-Yuan CHEN, Sang-Mao CHIU
  • Publication number: 20250176198
    Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.
    Type: Application
    Filed: January 30, 2025
    Publication date: May 29, 2025
    Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
  • Patent number: 12315857
    Abstract: An electronic device includes an object substrate, an electronic unit and an electrostatic discharge protective unit. The object substrate includes a bonding pad. The electronic unit includes an electrode bonding on the bonding pad. The electrostatic discharge protective unit is located in the object substrate and electrically connected to the bonding pad.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 27, 2025
    Assignee: Innolux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee
  • Publication number: 20250159975
    Abstract: An integrated circuit (IC) structure includes a first transistor and a second transistor. The first transistor includes a first active region and a first gate disposed on the first active region, in which the first gate has a first effective gate length along a first direction parallel to a lengthwise direction of the first active region. The second transistor includes a second active region and a second gate disposed on the second active region, and includes a plurality of gate structures arranged along the first direction and separated from each other, in which the second gate has a second effective gate length along the first direction, the second effective gate length is n times the first effective gate length, and n is a positive integer greater than 1.
    Type: Application
    Filed: January 16, 2025
    Publication date: May 15, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan CHEN, Hau-Tai SHIEH
  • Publication number: 20250155997
    Abstract: A touchpad device includes a substrate, a touch panel, a switch, a balancing assembly, and a triggering member. An inner surface of the touch panel facing the substrate has a central region. The switch is disposed between the substrate and the touch panel and corresponds to the central region. The balancing assembly is disposed between the touch panel and the substrate and includes a first balancing bar, a second balancing bar, a third balancing bar, and a fourth balancing bar. The triggering member has a top portion and a bottom portion, the bottom portion is leaned against end portions of a first swing bar of the first balancing bar, a second swing bar of the second balancing bar, a third swing bar of the third balancing bar, and a fourth swing bar of the fourth balancing bar which are adjacent to the switch, and the top portion contacts the switch.
    Type: Application
    Filed: September 17, 2024
    Publication date: May 15, 2025
    Inventors: Po-Hsin Li, Min-Yuan Chen, Wen-Yuan Lin
  • Patent number: 12298602
    Abstract: A contact lens product includes a multifocal contact lens and a buffer solution. The multifocal contact lens is immersed in the buffer solution. The multifocal contact lens includes a central region and at least one annular region. The annular region concentrically surrounds the central region, and a diopter of the annular region is different from a diopter of the central region. The multifocal contact lens is made of silicone hydrogel or hydrogel. The annular region closest to a periphery of the multifocal contact lens is a first annular region.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: May 13, 2025
    Assignee: LARGAN MEDICAL CO., LTD.
    Inventors: En-Ping Lin, Wei-Yuan Chen, Chun-Hung Teng
  • Patent number: 12302607
    Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.
    Type: Grant
    Filed: May 21, 2024
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Lo-Heng Chang, Li-Zhen Yu, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 12300605
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Patent number: 12300749
    Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Ching Wang, Wen-Yuan Chen, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20250143031
    Abstract: An electronic device is provided. The electronic device includes a substrate, a driving layer, a semiconductor element, an insulating layer, a first conductive element and a second conductive element. The driving layer is disposed on the substrate and includes a transistor. The semiconductor element is disposed on the driving layer. The insulating layer is disposed between the driving layer and the semiconductor element. The first conductive element passes through the insulating layer to be electrically connected to the semiconductor element. The second conductive element passes through the insulating layer to be electrically connected to the semiconductor element. Moreover, the semiconductor element is electrically connected to the driving layer through the first conductive element and the second conductive element.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Jia-Yuan CHEN, Tsung-Han TSAI, Kuan-Feng LEE
  • Publication number: 20250143037
    Abstract: An electronic device includes a substrate, a circuit layer, a first light emitting unit, a second light emitting unit, and a light conversion layer. The circuit layer is disposed on the substrate. The first and second light emitting units are disposed on the circuit layer and are respectively electrically connected to the circuit layer. The light conversion layer is disposed on the first and second light emitting units and includes a first light conversion unit overlapping the first light emitting unit and a second light conversion unit overlapping the second light emitting unit. The first and second light conversion units correspond to a first color. In a top view, an area of the first light emitting unit is smaller than an area of the second light emitting unit, and an area of the first light conversion unit is the same as an area of the second light conversion unit.
    Type: Application
    Filed: September 26, 2024
    Publication date: May 1, 2025
    Applicant: Innolux Corporation
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee