Patents by Inventor Yuan Chou

Yuan Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12275953
    Abstract: A method for screening host cells expressing a target protein is provided. The method includes the following steps: providing an expression vector, the expression vector including a promoter, a gene encoding a target protein and an FTH1 gene; transfecting the host cells with the expression vector; culturing the host cells in a medium; and adding iron ions to the medium, and screening the surviving host cells to obtain the host cells expressing the target protein. An expression vector and a method for establishing a cell line stably expressing an exogenous recombinant gene are also provided.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 15, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Ju Lin, Mei-Wei Lin, Min-Yuan Chou
  • Publication number: 20250081543
    Abstract: A semiconductor device comprises: a silicon carbide epitaxial layer. The silicon carbide epitaxial layer has: a p-type buried layer; and a junction field effect region in contact with the p-type buried layer in a gate region. The semiconductor device further comprises: a gate oxide layer on the silicon carbide epitaxial layer; a poly silicon layer on the gate oxide layer; an interlayer dielectric layer on the poly silicon layer; a first recess formed in the silicon carbide epitaxial layer by passing through the interlayer dielectric layer, the poly silicon layer and the gate oxide layer in a source region; and a second recess formed in the poly silicon layer in the gate region, wherein a bottom surface of the second recess is higher than a top surface of the gate oxide layer.
    Type: Application
    Filed: February 1, 2024
    Publication date: March 6, 2025
    Inventors: Yuan Liang LIU, Yen Chang CHEN, Yuan Chou CHANG, Yi Chen LEE
  • Patent number: 12241787
    Abstract: The present disclosure provides a microbolometer including a substrate, a readout circuit layer disposed above the substrate, a first vanadium oxide layer disposed above the readout circuit layer, a second vanadium oxide layer disposed on the first vanadium oxide layer, and an infrared absorbing layer disposed above the second vanadium oxide layer, in which an oxygen content of the second vanadium oxide is higher than that of the first vanadium oxide layer.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: March 4, 2025
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Chun-Yuan Chou
  • Publication number: 20250008693
    Abstract: A heat-dissipating element having a casing having a closed fluid space. At least a part of the fluid space is filled with a coolant fluid, and the coolant fluid is transformed between a liquid phase and a gas phase by an environment temperature transferred by the casing.
    Type: Application
    Filed: June 27, 2024
    Publication date: January 2, 2025
    Inventors: Tzu-Chia TAN, YAO-CHUN WANG, WEN-HUNG LIN, WEN-YUAN CHOU, PO-CHING LIN, SHANTI KARTIKA SARI
  • Publication number: 20240244834
    Abstract: A semiconductor device, including a first MOS device, a second MOS device, a first dielectric layer, a stop layer, and a second dielectric layer, is provided. The first MOS device and the second MOS device are located on a substrate. The first dielectric layer is beside the first MOS device and the second MOS device. The stop layer is disposed on the first dielectric layer. The second dielectric layer covers the stop layer. The thickness of the second dielectric layer above the first MOS device is greater than the thickness of the second dielectric layer above the second MOS device.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 18, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Mei-Yuan Chou, Yoshinori Tanaka
  • Patent number: 12021059
    Abstract: A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: June 25, 2024
    Assignee: INTEGRATED SILICON SOLUTION INC.
    Inventors: Hsingya Arthur Wang, Sheng-Yuan Chou, Yu-Ting Wang, Wan-Yi Chang
  • Publication number: 20240127109
    Abstract: A federated learning method includes: providing importance parameters and performance parameters by client devices respectively to a central device, performing a training procedure by the central device, wherein the training procedure includes: selecting target devices from the client devices according to a priority order associated with the importance parameters, dividing the target devices into training groups according to a similarity of the performance parameters, notifying the target devices to perform iterations according to the training groups respectively to generate trained models, transmitting the trained models to the central device, and updating a global model based on the trained models, performing the training procedure again or outputting the global model to the client devices based on a convergence value of the global model and the number of times of performing the training procedure.
    Type: Application
    Filed: November 10, 2022
    Publication date: April 18, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Ping Feng WANG, Chiun Sheng HSU, Chi-Yuan CHOU, Fu-Chiang CHANG
  • Publication number: 20240118178
    Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Applicant: FULLHOPE BIOMEDICAL CO., LTD.
    Inventors: Jan-Mou Lee, Li-Jen Liao, Yen-Ling Chiu, Chih-Hao Fang, Kai-Yuan Chou, Pei-Hsien Liu, Cheng-Yun Lee
  • Patent number: 11943913
    Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: March 26, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Te-Hsuan Peng, Kai Jen, Mei-Yuan Chou
  • Patent number: 11871510
    Abstract: A conductive pattern has been disclosed. The conductive pattern includes a pair of conductive traces. Each of the conductive traces comprises a linear portion and a terminal portion. The terminal portions are arranged adjacent to each other and comprises a pair of circular arc profile with a pair of complementary notches facing toward each other.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: January 9, 2024
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu, Feng-Hua Deng, Ming-Fang Chen
  • Publication number: 20230416362
    Abstract: Antibodies and antigen-binding fragments that bind to TIGIT are disclosed. The disclosure further relates to methods and compositions for use in treating an immune-related disease (e.g., a cancer or an infection or infectious disease) by administering a composition disclosed herein.
    Type: Application
    Filed: May 17, 2023
    Publication date: December 28, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Min-Yuan CHOU, Li-Tsen LIN, Chung-Yuan SUN, Ya-Ping LAI, Chin-Pen LAI, Ssu-Yuan WU, Mei-Wei LIN
  • Patent number: 11822331
    Abstract: The present invention relates to an environmental coverage oriented motion system. The system includes a rangefinder module configured to measure a distance in real time; an odometry module configured to measure a velocity or a position in real time; a powered vehicle carrying the rangefinder module and the odometry module; and a controller module carried by the powered vehicle, configured to receive one of the distance, the velocity and the position, performing an environmental coverage oriented motion scheme based on one of the distance, the velocity and the position to select a plurality of positions, and commanding the powered vehicle to move among the plurality of positions.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 21, 2023
    Assignee: National Central University
    Inventors: Kuo-Shih Tseng, Chih-Yuan Chou
  • Publication number: 20230342385
    Abstract: A method for extracting text relevant to a particular topic from a document to generate a narrower, condensed, more specific, and smaller version obtains information as to the text of a large document and searches the text information of the document based on first keywords to extract first pages. The first pages are inputted into a predetermined learning model to extract second keywords from the first pages, and the first keywords and the second keywords are integrated to obtain third keywords. The method further searches the text of the first pages based on the third keywords to extract second pages and a determination is made as to whether the second pages meet a predetermined page standard. If yes, the second pages are integrated and output. An electronic device and a non-transitory storage medium are also disclosed.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 26, 2023
    Inventors: JIAN-CAI CHEN, JUN-CONG GONG, GUANG-LIN HU, HOU-YUAN CHOU
  • Patent number: 11788129
    Abstract: A GAPDH nucleic acid detection kit includes a primer set for detecting GAPDH nucleic acid. The primer set for detecting GAPDH nucleic acid includes a forward inner primer for GAPDH nucleic acids, a forward outer primer for GAPDH nucleic acids, a backward inner primer for GAPDH nucleic acids and a backward outer primer for GAPDH nucleic acids. The primer set for detecting GAPDH nucleic acid is used in a loop-mediated isothermal amplification (LAMP).
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 17, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Min-Yuan Chou, Kuang-Chi Cheng, Ming-Hua Yang, Jiun-Lin Guo
  • Publication number: 20230255020
    Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Te-Hsuan PENG, Kai JEN, Mei-Yuan CHOU
  • Publication number: 20230251140
    Abstract: The present disclosure provides a microbolometer including a substrate, a readout circuit layer disposed above the substrate, a first vanadium oxide layer disposed above the readout circuit layer, a second vanadium oxide layer disposed on the first vanadium oxide layer, and an infrared absorbing layer disposed above the second vanadium oxide layer, in which an oxygen content of the second vanadium oxide is higher than that of the first vanadium oxide layer.
    Type: Application
    Filed: March 18, 2022
    Publication date: August 10, 2023
    Inventor: Chun-Yuan CHOU
  • Patent number: 11667709
    Abstract: Antibodies and antigen-binding fragments that bind to TIGIT are disclosed. The disclosure further relates to methods and compositions for use in treating an immune-related disease (e.g., a cancer or an infection or infectious disease) by administering a composition disclosed herein.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: June 6, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Yuan Chou, Li-Tsen Lin, Chung-Yuan Sun, Ya-Ping Lai, Chin-Pen Lai, Ssu-Yuan Wu, Mei-Wei Lin
  • Publication number: 20230145177
    Abstract: A federated learning method and a federated learning system based on mediation process are provided. The federated learning method includes: dividing a plurality of client devices into a plurality of mediator groups, and generate a plurality of mediator modules; configuring a server device to broadcast initial model weight data to the plurality of mediator modules; configuring the plurality of mediator modules to execute a sequential training process for the plurality of mediator groups to train a target model and generate trained model weight data; configuring the server device to execute a weighted federated averaging algorithm to generate global model weight data; and configuring the server device to set the target model with the global model weight data to generate a global target model.
    Type: Application
    Filed: November 25, 2021
    Publication date: May 11, 2023
    Inventors: PING-FENG WANG, CHIUN-SHENG HSU, JERRY CHI-YUAN CHOU
  • Publication number: 20230084548
    Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer formed on the sidewall and the bottom surface of a trench in the substrate, a barrier layer formed in the trench and on the sidewall and the bottom surface of the gate dielectric layer, a first work function layer formed in the trench and including a main portion and a protruding portion, a second work function layer formed at opposite sides of the protruding portion, and an insulating layer formed in the trench and on the protruding portion of the first work function layer and the second work function layer. The barrier layer surrounds the main portion of the first work function layer. The area of the top surface of the protruding portion is less than the area of the bottom surface of the protruding portion.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Te-Hsuan PENG, Kai JEN, Mei-Yuan CHOU
  • Patent number: 11596067
    Abstract: An apparatus having stacked circuit boards has been disclosed. The apparatus includes a main circuit board and a sub circuit board disposed over the main circuit board. A plurality of sub components disposed on a bottom face of the sub circuit board penetrates through main circuit board and extends towards a bottom face of the main circuit board. In this say, a compact apparatus is produced.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: February 28, 2023
    Assignee: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD.
    Inventors: Hou-Yuan Chou, Yi-Chih Wu