Abstract: An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.

Abstract: A 3D printer including a machine platform, a container, at least one stirring element and a driving element is provided. The container contains a liquid forming material, and is movably assembled to the machine platform. The stirring element is disposed in the container to move along with the container, and has a motion mode of moving away from or moving close to a bottom of the container. The driving element is fixed on the machine platform and extends into the container. The driving element and the stirring element are mutually located on moving paths of each other. During a moving process of the container, the driving element and the stirring element lean against each other to trigger the motion mode of the stirring element to move away from or move close to the bottom of the container, so as to stir the liquid forming material in the container.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A circuit board includes a board defining a holding slot and a connector. The connector includes a conductive column and a pad fixed to one end of the conductive column. The pad is received within the holding slot. The conductive column is fixed within the board. The pad is soldered to a connecting portion of an electrical component. The pad defines a first through hole receiving solder when the connecting portion of the electrical component is soldered to the pad.

Abstract: A wireless communication device that includes an antenna module, a first communication circuit and a second communication circuit is provided. The first communication circuit performs communication by using a first communication protocol and transmits a test signal via the antenna module. The second communication circuit performs communication by using a second communication protocol and receives the test signal to calculate an isolation index based on an actual received power thereof. The second communication circuit determines that the antenna module includes two antennas when the isolation index is smaller than a threshold value to operate the first and the second communication circuits under a dual-antenna operation mode. The second communication circuit determines that the antenna module includes one antenna when the isolation index is not smaller than the threshold value to operate the first and the second communication circuits under a shared-antenna operation mode.

Abstract: The present invention relates to a method for producing multivalent Fab fragments. In particular, the invention relates to a method for the generation of trimeric Fab fragments by co-expression of a gene construct comprising a heavy chain portion of a Fab fragment and an in-frame fused collagen-like peptide, and a gene construct consisting of a light chain portion of an IgG in mammalian cells. Uses of molecules generated using the method of the invention are also described.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A method for calibrating light is adapted to a 3D object generating apparatus including a housing, an optical-transparent component, and a laser light generator. The housing has an accommodating space and an opening communicating with the accommodating space. The optical transparent component is arranged on the opening, and the laser light generator is arranged within the accommodating space. The method includes the following steps: providing a first photodetector and a controller, the controller is electrically connected to the first photodetector and the laser light generator; using the controller to drive the laser light generator to generate the light and perform a scanning procedure; and stopping the scanning procedure when the first photodetector detects the light generated by the laser light generator, and then performing a 3D object generating procedure in the working region by moving the laser light generator with a preset distance.

Abstract: A keyboard apparatus and a detection method for status of keys thereof are provided. The detection method includes the following steps. First lines of a key module in the keyboard apparatus are driven to a first potential. Whether any key on each of second lines in the key module is pressed is detected as a first detection result. The second lines are driven to the first potential. Whether any key on each of the first lines is pressed is detected as a second detection result. One of the first lines is sequentially selected, and a press status of each key on the selected first line is scanned through the second lines so as to generate a coarse scan result. The press status of each key is obtained and whether the press status is misjudged is determined according to the first and the second detection results and the coarse scan result.

Abstract: A system for prefetching data for a processor includes a processor core, a memory configured to store information for use by the processor core, a cache memory configured to fetch and store information from the memory, and a prefetch circuit. The prefetch circuit may be configured to issue a multi-group prefetch request to retrieve information from the memory to store in the cache memory using a predicted address. The multi-group prefetch request may include a depth value indicative of a number of fetch groups to retrieve. The prefetch circuit may also be configured to generate an accuracy value based on a cache hit rate of prefetched information over a particular time interval, and to modify the depth value based on the accuracy value.

Abstract: An system for prefetching data for a processor includes a processor core, a memory, a cache memory, and a prefetch circuit. The memory may be configured to store information for use by the processor core. The cache memory may be configured to issue a fetch request for information from the memory for use by the processor core. The prefetch circuit may be configured to issue a prefetch request for information from the memory to store in the cache memory using a predicted address, and to monitor, over a particular time interval, an amount of fetch requests from the cache memory and prefetch requests from the prefetch circuit. The prefetch circuit may also be configured to disable prefetch requests from the memory for a subsequent time interval in response to a determination that the amount satisfies a threshold amount.

Abstract: A 3D object generating apparatus includes an optical-transparent, a laser light generating module, and a controller. The laser light generating module includes a light emitter for outputting a spot beam, a polygon mirror, a flat-field convergent lens, and a flat-field optical sensor. The polygon mirror directs the spot beam into a linear beam. The flat-field convergent lens is positioned between the laser light generating module and the optical-transparent component, and a flat-field scanning route is formed after the linear beam passed through the flat-field convergence lens. The flat-field optical sensor is positioned on the flat-field scanning route senses an optical power of the linear beam and generates a sensed signal. The controller is electrically connected to the laser light generating module and the flat-field optical sensor, and receives the sensed signal and calibrates the optical power of the spot beam based on the sensed signal.

Abstract: A collagen scaffold domain, including a collagenous or collagen-like domain, which directs self-trimerization is provided. The collagen scaffold domain can be fused to one or more heterologous domains, such as an antibody domain. Methods for generating and using the scaffold domains and fusion proteins are also provided.

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.

Abstract: A system for controlling key access using a phone and internet-connected key box device. The key box device hangs or mounts on a fixture and controls key access to visitors. Visitors may unlock a chamber in a key device for key access by calling the phone number on the key box device display and passing an authentication process during a scheduled time. The key box device owner may monitor and remotely control access to the key box and its key chamber via a software application on cloud computing services that interfaces with operations programmed into a circuit board in the key box device.

Abstract: A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.

Abstract: A server and a cloud computing resource optimization method thereof for cloud big data computing architecture are provided. The server runs a dynamic scaling system to perform the following operations: receiving a task message; executing a profiling procedure to generate a profile based on an to-be-executed task recorded in the task message; executing a classifying procedure to determine a task classification of the to-be-executed task; executing a prediction procedure to obtain a plurality of predicted execution times corresponding to a plurality of computing node numbers, a computing node type and a system parameter of the to-be-executed task; executing an optimization procedure to determine a practical computing node number of the to-be-executed task; and transmitting an optimization output message to a management server to make the management server allocate at least one data computing system to execute a program file of the to-be-executed task.

Abstract: An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.

Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes patterning a semiconductor substrate to form a fin structure. The method also includes forming a sacrificial material over the fin structure. The method further includes forming spacer elements adjoining sidewalls of the sacrificial material. Furthermore, the method includes removing the sacrificial material so that a trench is formed between the spacer elements. The method also includes forming a gate dielectric layer in the trench. The method further includes forming a work function layer in the trench to cover the gate dielectric layer. In addition, the method includes depositing a tungsten bulk layer with a precursor to fill the trench. The precursor includes a tungsten-containing material that is substantially free of fluoride.