Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: An apparatus is disclosed, the apparatus including a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.

Abstract: A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.

Abstract: A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.

Abstract: A humanized monoclonal antibody against the CD34 surface antigen is provided in the present disclosure. The humanized monoclonal antibody includes a light chain variable region and a heavy chain variable region. In which, a nucleotide sequence encoding the amino acid sequence for the light chain variable region comprises a nucleotide sequence which encodes the amino acid sequence of SEQ ID No. 9 or an amino acid sequence with at least 80% sequence identity to the sequence of SEQ ID No. 9, and a nucleotide sequence encoding the amino acid sequence for the heavy chain variable region comprises a nucleotide sequence which encodes the amino acid sequence of SEQ ID No. 10 or an amino acid sequence with at least 80% sequence identity to the sequence of SEQ ID No. 10.

Abstract: A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries. The processor may be configured to access data from a subset of the plurality of pages dependent upon a first virtual address. The TLB may be configured to compare the first virtual address to respective address information included in each entry of the plurality of entries. The TLB may be further configured to add a new entry to the plurality of entries in response to a determination that the first virtual address fails to match the respective address information included in each entry of the plurality of entries. The new entry may include address information corresponding to at least two pages of the subset of the plurality pages.

Abstract: A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. An interlayer insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so that a space is formed. A gate dielectric layer is formed in the space. A first metal layer is formed over the gate dielectric in the space. A second metal layer is formed over the first metal layer in the space. The first and second metal layers are partially removed, thereby reducing a height of the first and second metal layers. A third metal layer is formed over the partially removed first and second metal layers.

Abstract: A system for controlling key access using a phone and internet-connected key box device. The key box device hangs or mounts on a fixture and controls key access to visitors. Visitors may unlock a chamber in a key device for key access by calling the phone number on the key box device display and passing an authentication process during a scheduled time. The key box device owner may monitor and remotely control access to the key box and its key chamber via a software application on cloud computing services that interfaces with operations programmed into a circuit board in the key box device.

Abstract: A 3D object generating apparatus includes an optical-transparent, a laser light generating module, and a controller. The laser light generating module includes a light emitter for outputting a spot beam, a polygon mirror, a flat-field convergent lens, and a flat-field optical sensor. The polygon mirror directs the spot beam into a linear beam. The flat-field convergent lens is positioned between the laser light generating module and the optical-transparent component, and a flat-field scanning route is formed after the linear beam passed through the flat-field convergence lens. The flat-field optical sensor is positioned on the flat-field scanning route senses an optical power of the linear beam and generates a sensed signal. The controller is electrically connected to the laser light generating module and the flat-field optical sensor, and receives the sensed signal and calibrates the optical power of the spot beam based on the sensed signal.

Abstract: A keyboard apparatus and a detection method for status of keys thereof are provided. The detection method includes the following steps. First lines of a key module in the keyboard apparatus are driven to a first potential. Whether any key on each of second lines in the key module is pressed is detected as a first detection result. The second lines are driven to the first potential. Whether any key on each of the first lines is pressed is detected as a second detection result. One of the first lines is sequentially selected, and a press status of each key on the selected first line is scanned through the second lines so as to generate a coarse scan result. The press status of each key is obtained and whether the press status is misjudged is determined according to the first and the second detection results and the coarse scan result.

Abstract: An apparatus includes a buffer configured to store a plurality of instructions previously fetched from a memory, wherein each instruction of the plurality of instructions may be included in a respective thread of a plurality of threads. The apparatus also includes control circuitry configured to select a given thread of the plurality of threads dependent upon a number of instructions in the buffer that are included in the given thread. The control circuitry is also configured to fetch a respective instruction corresponding to the given thread from the memory, and to store the respective instruction in the buffer.

Abstract: A method for calibrating light is adapted to a 3D object generating apparatus including a housing, an optical-transparent component, and a laser light generator. The housing has an accommodating space and an opening communicating with the accommodating space. The optical transparent component is arranged on the opening, and the laser light generator is arranged within the accommodating space. The method includes following steps: providing a first photodetector and a controller, the controller is electrically connected to the first photodetector and the laser light generator; using the controller to drive the laser light generator to generate the light and perform a scanning procedure; and stopping scanning procedure when the first photodetector detecting the light generated by the laser light generator, and then performing a 3D object generating procedure in the working region by moving the laser light generator with a preset distance.

Abstract: A system includes a memory, a cache including multiple cache lines; and a processor. The processor may be configured to retrieve, from a first cache line, a first instruction to store data in a memory location at an address in the memory. The processor may be configured to retrieve, from a second cache line, a second instruction to read the memory location at the address in the memory. The second instruction may be retrieved after the first instruction. The processor may be configured to execute the second instruction at a first time dependent upon a value of a first entry in a table, wherein the first entry is selected dependent upon a value in the second cache line. The processor may be configured to execute the first instruction at a second time, after the first time, and invalidate the second instruction at a third time, after the second time.

Abstract: A friction stir welding device, provided for welding stacked metallic boards together, includes a mounting seat and a plurality of friction-stir tools. The mounting seat is defined with a rotational axis-direction. Each friction-stir tool has a shoulder portion and a stirring probe protruded from the shoulder portion. The friction-stir tools are arranged in the rotational axis-direction and disposed on a bottom surface of the mounting seat. The friction-stir tools can rotate along the rotational axis-direction. When a relative linear motion is applied between the friction-stir tools and the stacked metallic boards, the shoulders of the friction-stir tools produce stirring-coverage zones which are overlapped partially along the linear movement direction, so that the stirring-coverage zones by the friction-stir tools form a planar welding zone. The present disclosure also provides a method of friction stir welding for welding stacked metallic boards together.

Abstract: A heat-dissipating device includes a base and a plurality of heat-dissipating members. The base is formed with a plurality of joint holes. Each heat-dissipating member has an inserting section and an exposed section connected with the inserting section. The inserting sections are inserted into the joint holes in a close fit manner, respectively. The exposed sections are exposed outside a top surface of the base. The ends of the inserting sections and the bottom surface of the base are welded by a friction stir welding (FSW) manner with a solid-state joining structure. The present disclosure also provides a method for manufacturing a heat-dissipating device, which joins the ends of the inserting sections and the bottom surface of the base by a friction stir welding manner.

Abstract: A system may include a memory that includes a plurality of pages, a processor, and a translation lookaside buffer (TLB) that includes a plurality of entries. The processor may be configured to access data from a subset of the plurality of pages dependent upon a first virtual address. The TLB may be configured to compare the first virtual address to respective address information included in each entry of the plurality of entries. The TLB may be further configured to add a new entry to the plurality of entries in response to a determination that the first virtual address fails to match the respective address information included in each entry of the plurality of entries. The new entry may include address information corresponding to at least two pages of the subset of the plurality pages.

Abstract: A system for controlling key access using a phone and Internet-connected key box device. The key box device comprises a SIM card programmed with a unique phone number associated with the key box. Calling the phone number using any phone will provide access to the key box. A cloud computing software application then interfaces with operations programmed into a circuit board. A user then unlocks a key chamber by calling the number at a scheduled time. The key box device owner monitors and controls access to the box and its key chamber via the software application.

Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.