Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for row hammer counter resets. Repeated access to an aggressor word line may cause increased data degradation in nearby victim word lines of the memory. The access count value of a given word line may be stored in counter memory cells positioned along that word line. The count values may be randomly or pseudo-randomly initialized. In some examples, a memory device may utilize residual charges that are present on the counter cells during start-up to initialize the counter memory cells. In some other examples, a memory device may utilize threshold voltage compensation (VtC) settings at start-up to initialize the counter memory cells. In some other examples, a memory device may utilize a combination of the residual charges that are present on the counter cells and VtC settings on start-up to initialize the counter memory cells.

Abstract: A microelectronic device is disclosed that includes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices and extending in a first direction; and word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and the word lines extend into word line exit regions. The word line exit regions are horizontally alternating with the array regions in the second direction; and sub word line driver sections are overlapping and above, and in electrical communication with the word line exit regions. Electrical communication between word lines in the word line exit regions and the sub word line driver sections vertically coupled with a vertical word line contact and other interconnections is laterally bounded within socket regions delineated by horizontal boundaries of the word line exit regions.

Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

Abstract: Memory devices direct refresh management (DRFM) attack identification. A DRFM logic circuit receives DRFM aggressor address and compares it to a previous DRFM aggressor address. If there is not a match, then a DRFM operation is performed. If there is a match, then the DRFM operation may be skipped. This may prevent repeated DRFM operations from being performed on a same DRFM aggressor address.

Abstract: A work distribution platform is disclosed that is coupled with client devices associated with workers. The work distribution may include matching systems to match workers with orders. An example matching system is a worker offering system, with which the work distribution platform provides orders to workers so that the workers may submit offers to perform the order. The work distribution platform may include a plurality of matching systems, each of which may perform a different process for matching orders with workers and each of which may be used by the work distribution platform.

Abstract: Methods, systems, and apparatus are provided for generating an image. A personalized text prompt is generated by processing an input embedding using a transformer model followed by a first fully connected neural network. The input embedding comprises a multi-dimensional embedding vector associated with a user profile and a plurality of user items. A scored label set is generated identifying a user's preferences by processing a set of attributes for the plurality of user items using a second fully connected neural network. The image is generated by processing the personalized text prompt and the scored label set using a diffusion model.

Abstract: Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.

Abstract: Apparatuses and methods per-row count based refresh target identification. A memory device stores count values associated with the word lines. An aggressor detector circuit stores a maximum of the count values and a row address associated with the maximum count value. Responsive to a targeted refresh signal, the stored count value is compared to a threshold. If the count value has crossed the threshold, then a targeted refresh operation may be performed on one or more refresh addresses based on the stored address, and the count value may be reset.

Abstract: A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A radiation inspection system including: a radiation imaging device, which includes at least one radiation source and at least one detector module, has a CT inspection mode and a DR inspection mode, and is configured to perform radiation inspection on an object to be inspected passing through an inspection channel; a conveying device, which includes a conveying device main body, and a primary-secondary motor in drive connection with the conveying device main body, including a main motor, a sub-motor, and a speed reducer; and a controller in signal connection with the radiation imaging device and the primary-secondary motor, configured such that when the radiation imaging device is in the CT inspection mode, the conveying device main body is in drive connection with the sub-motor, and in the DR inspection mode, the conveying device main body is in drive connection with the main motor.

Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

Abstract: Some embodiments include an integrated assembly having a CMOS-containing base containing wordline-driver-circuitry. The wordline-driver-circuitry is subdivided amongst horizontally-extending sub-wordline-driver (SWD) units. Memory cells are over the base, and are arranged in vertically-extending rows. Each of the memory cells includes an access device and a storage element coupled with the access device. Wordlines extend vertically along the rows. Each of the SWD units is associated with at least two of the wordlines and is configured to simultaneously activate the associated wordlines.

Abstract: A system and method for lead conversion using conversational virtual avatar is disclosed. System comprising processor causes Conversation Virtual Avatar Platform (CVAP) to receive, for first entity, from lead prioritization engine, leads applicable to first entity via lead repository based on scores associated with respective leads. Processor causes CVAP to receive, through conversation management engine (CME) configured in CVAP, from leads, responses to questions pertaining to product attributes and information pertaining to lead.

Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

Abstract: Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

Abstract: An artificial intelligence (AI) technique to process and query data pertaining to an enterprise. A user raises a request which is processed to predict a knowledge context area based on a predetermined structure of the enterprise. The knowledge context area is predicted from multiple knowledge context areas, on the basis of the received user request and a conversation history of the user in past. Further, a knowledge database is selected from multiple knowledge databases based on the user request and the predicted knowledge context. The knowledge databases include preprocessed data from multiple data sources. The knowledge database is queried on the basis of the user request related to the knowledge context to obtain a result and the result is then displayed as an output.

Abstract: A system and method for video compression divides colors of all pixel points of a target video frame into R, G, and B values, and all pixels are placed in a three-dimensional coordinate system to establish a correspondence between each pixel point and the coordinate position. Fuzzy recombination and division are performed on all pixel blocks and pixel points with similar RGB values are divided into pixel blocks to obtain a first target pixel block. Pixel blocks with same RGB values but with coordinates which are not close to the first target pixel block are extracted and divided to obtain a second target pixel block. An area enveloping the second target pixel block is extracted, and vector changes of all dynamic pixel points on the enveloping line are traversed and analyzed to determine a minimum compression change block for compression process.

Abstract: Apparatuses and techniques for implementing aspects of proactive usage-based disturbance mitigation based on resource availability are described. In an example aspect, usage-based disturbance circuitry of a memory device performs usage-based disturbance mitigation based on multiple criteria. A primary criterion is associated with normal usage-based disturbance mitigation and can enable the memory device to balance power consumption with usage-based disturbance mitigation. At least one secondary criterion is less strict compared to the primary criterion. While a resource is available, the usage-based disturbance circuitry can proactively mitigate usage-based disturbance based on activated rows that satisfy the secondary criterion but don't yet satisfy the primary criterion. With these preemptive measures, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation while the resource is available.

Abstract: Apparatuses and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation. In an example aspect, usage-based disturbance circuitry of a memory device utilizes a threshold that varies over time for detecting conditions associated with usage-based disturbance. By utilizing the time-varying threshold, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation. In particular, the time-varying threshold can spread out the refreshing of rows over a longer time period. This enables the memory device to have sufficient resources to service other memory requests while also mitigating usage-based disturbance. In example implementations, the threshold is at least partially randomized, which can make it challenging for a malicious actor to identify and overcome the usage-based disturbance mitigation techniques.