Patents by Inventor YUAN HUANG

YUAN HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086612
    Abstract: An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Po-Hsiang HUANG, Fong-Yuan CHANG, Clement Hsingjen WANN, Chih-Hsin KO, Sheng-Hsiung CHEN, Li-Chun TIEN, Chia-Ming HSU
  • Publication number: 20240089607
    Abstract: An image sensing device and a control device of an illumination device thereof are provided. The control device includes a control circuit, an operation circuit, and multiple driving signal generators. The control circuit generates multiple control signals. The operation circuit performs a logical operation on the control signals and an image capturing signal to generate multiple operation results. The driving signal generator respectively provides multiple driving signals to the illumination device according to the operation results, and the driving signals respectively have multiple different output powers.
    Type: Application
    Filed: May 29, 2023
    Publication date: March 14, 2024
    Applicant: HTC Corporation
    Inventors: Chao Shuan Huang, Sheng-Long Wu, Yu-Jui Hsu, Shih-Yao Tsai, Tun-Hao Chao, Sen-Lin Chung, Chih Pin Chung, Chih-Yuan Chien, Shih Hong Sun
  • Publication number: 20240090215
    Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Yuan-Huang WEI, Chien-Hsien WU, Hsiu-Han LIAO
  • Publication number: 20240090336
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin YANG, Chung-Te LIN, Sheng-Yuan CHANG, Han-Ting LIN, Chien-Hua HUANG
  • Publication number: 20240082160
    Abstract: An amlodipine dry suspension, comprising a diluent, a suspending aid, etc. and being free of surfactants. A preparation method therefor comprises the following steps: a) preparing an aqueous mixture 1 containing amlodipine besylate by using a high-speed homogenization method; b) adding sodium benzoate to the mixture 1, and homogenizing same at a high speed to obtain a mixture 2; and c) granulating the mixture 2 and other components, and then drying same. The raw materials are homogenized and mixed at a high speed, no surfactant is added during the preparation, amlodipine is fully wetted by using a high-speed homogenization process, prescription components are simplified, and the amlodipine dry suspension is more suitable for children to use. Compared with ultrasonic stirring, scaled-up and industrial production are easier to realize for the high-speed homogenization process, and at the same time, the preparation is good in stability and convenient to carry.
    Type: Application
    Filed: December 31, 2021
    Publication date: March 14, 2024
    Inventors: Hanxiong Li, Xianzhu Wang, Weitang Chen, Yuan Chen, Ping Guo, Yongyi Wu, Yongmei Qin, Hongxue Huang, Li Wang
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11930475
    Abstract: A wireless terminal determines a tracking area code (TAC) from a geographic position of the wireless terminal. From the TAC, the wireless terminal determines the tracking area identity based on an indication from the network-side regarding whether or not geographic position based tracking area identity determination is to be used or not. In some implementations, the network-side is a satellite cell that is configured to provide wireless connectivity to the wireless terminal.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 12, 2024
    Assignee: ZTE Corporation
    Inventors: Yuan Gao, He Huang, Jianwu Dou
  • Publication number: 20240079230
    Abstract: A plasma-assisted annealing system includes a high temperature furnace, a plasma-induced dissociator and a connecting duct. The plasma-induced dissociator is provided to dissociate a working gas and exhaust the dissociated working gas from its working gas outlet. Both ends of the connecting duct are connected to the working gas outlet of the plasma-induced dissociator and a gas inlet of the high temperature furnace, respectively. The working gas dissociated in the plasma-induced dissociator is introduced into the high temperature furnace via the connecting duct.
    Type: Application
    Filed: December 12, 2022
    Publication date: March 7, 2024
    Inventors: Wei-Chen Tien, Cheng-Yuan Hung, Chang-Sin Ye, Chun-Kai Huang, Yii-Der Wu
  • Publication number: 20240079268
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: Chih-Hui Huang, Cheng-Hsien Chou, Cheng-Yuan Tsai, Kuo-Ming Wu, Sheng-Chan Li
  • Publication number: 20240078441
    Abstract: A method for knowledge representation and deduction of service logic includes: generating, based on a knowledge representation model, a semantic graph corresponding to conceptual-layer service logic, where the semantic graph includes one or more types of nodes and edges for connecting the one or more types of nodes, and the nodes include at least a node of a variable type; generating, based on the semantic graph and a physical table to which a service object is mapped, an instance graph, where the instance graph includes the nodes and edges in the semantic graph; generating executable code based on a service logic relationship between the nodes in the instance graph; and determining, based on the executable code and a data instance corresponding to a node whose in-degree is 0 in the instance graph, a data instance corresponding to each node in the instance graph.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Inventors: Rong Duan, Kangxing Hu, Wenwen Huang, Yuan Yuan, Wen Peng, Chunxi Liu, Qinjie Yang, Xiaoliang Yin, Shufan Li
  • Publication number: 20240077564
    Abstract: A method of using NC-MRA to generate pelvic veins images and measure rate of blood flow includes subjecting a lay patient to undergo magnetic resonance scan in cooperation with an ECG monitor and a respiration monitor; scanning coronary sections and transverse sections of kidney veins, lower cavity veins, common iliac veins, and external iliac veins to generate two-dimensional images wherein the two-dimensional images use balanced turbo field echo wave sequence; scanning coronary sections of common cardinal veins of abdominal cavity to generate three-dimensional images wherein the three-dimensional images use fast spin-echo short tau inversion recovery wave sequence and sample signals when the ECG monitor monitors myocardial contractility; and using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Chang Gung Memorial Hospital, Chiayi
    Inventors: Chien-Wei Chen, Yao-Kuang Huang, Chung-Yuan Lee, Yeh-Giin Ngo, Yin-Chen Hsu
  • Patent number: 11918635
    Abstract: A method and a platform for detecting an immunogenicity of a tumor neoantigen are provided. Specifically, the detection method includes the following steps: culturing human peripheral blood monocytes ex vivo for 13 days, adding an antigenic peptide fragment of human influenza virus and stimulating and activating cytokines, antigenic peptides, and immunoadjuvants during the 13 days, and finally conducting enzyme-linked immunospot (ELISPOT) chromogenic reaction and instrument-based scanning, counting, and analysis to detect the immunogenicity of tumor neoantigen. An application of the detection method and platform in biomedicine is provided. Compared with the prior art, the detection method and platform have advantages and characteristics of a short detection period, high convenience, low consumption of experimental cells, and low detection cost. Therefore, the detection method and platform can be used for ex vivo high-throughput assay for the immunogenicity of the tumor neoantigen.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: March 5, 2024
    Assignees: NeoCura Bio-Medical Technology Co., Ltd, Beijing Neocurna Biotechnology corporation, Shenzhen Neocurna Biotechnology corporation
    Inventors: Youdong Pan, Qi Song, Ji Wan, Jun-Yuan Huang, An Xiao, Gang Liu, Ying Wen
  • Patent number: 11923271
    Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Noor E. V. Mohamed, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
  • Patent number: 11923302
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20240068043
    Abstract: Provided is a method for diagnosing and monitoring progression of cancer or effectiveness of a therapeutic treatment. The method includes detecting a methylation level of at least one gene in a biological sample containing circulating free DNA. Also provided are primer pairs and probes for diagnosis or prognosis of cancer in a subject in need thereof.
    Type: Application
    Filed: March 1, 2022
    Publication date: February 29, 2024
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsing-Chen TSAI, Chong-Jen YU, Hsuan-Hsuan LU, Shu-Yung LIN, Yi-Jhen HUANG, Chen-Yuan DONG
  • Publication number: 20240069912
    Abstract: A method for identifying hard-coded strings in source code is disclosed. In one embodiment, such a method parses source code and associated localization resource files to identify hard-coded strings and their associated context. The method provides a confidence score for each hard-coded string that indicates whether the hard-coded string is translatable or non-translatable. Based on the confidence score for each hard-coded string, the method transforms each hard-coded string into a single equivalence word. The method then prepares training data by tagging the hard-coded strings in the source code and associated localization resource files as one of translatable and non-translatable. The method then trains a parts-of-speech (POS) tagging model using the training data. At runtime, the method fetches potential hard-coded strings and tags each hard-coded string as one of translatable and non-translatable using the POS tagging model. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Applicant: International Business Machines Corporation
    Inventors: Jin Shi, Chih-Yuan Lin, Shu-Chih Chen, Pei-Yi Lin, Chao Yuan Huang
  • Publication number: 20240071865
    Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Inventors: Xinyu Bao, Lee-Chung Lu, Jyh Chwen Frank Lee, Fong-Yuan Chang, Sam Vaziri, Po-Hsiang Huang
  • Publication number: 20240070589
    Abstract: A method of engineering forecast and analysis is provided. The method includes: generating a forecasting model based on financial or business information obtained through a user interface, where the forecasting model expresses a logical determining and/or calculation rule based on a structure of a high-order directed graph and by using a plurality of nodes, attributes of the plurality of nodes, and a relationship between every two of the plurality of nodes, and the forecasting model expresses a forecasting path through a directed edge between the nodes; and configuring a common attribute of the forecasting model, an attribute of the forecasting path, and a personalized attribute of the node based on instantiation configuration information.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Inventors: Rong Duan, Yuan Yuan, Kangxing Hu, Chunxi Liu, Wenwen Huang, Wen Peng
  • Publication number: 20240069275
    Abstract: A method of wavelength tuning in a silicon photonics circuit includes receiving a bus waveguide, a ring resonator optically coupled to the bus waveguide, and a dielectric layer over the bus waveguide and over the ring resonator. The method further includes performing a first heat process at a first temperature to heat up the dielectric layer, where the first heat process shifts an initial resonance wavelength of the ring resonator to a first resonance wavelength shorter than the initial resonance wavelength. The first heat process permanently shifts the initial resonance wavelength to the first resonance wavelength, the first resonance wavelength being a wavelength when no heat is being applied to the ring resonator.
    Type: Application
    Filed: April 11, 2023
    Publication date: February 29, 2024
    Inventors: Beih-Tzun Lin, Chi-Yuan Shih, Feng Yuan, Shih-Fen Huang
  • Publication number: 20240071731
    Abstract: A substrate processing apparatus, comprising: a processing chamber having a plasma intake wall configured to receive plasma from a remote plasma source (RPS) and a surrounding wall having an inner surface defining an interior volume for receiving a substrate; and a substrate support having a substrate supporting surface facing the plasma intake wall and elevatably arranged in the interior volume of the processing chamber. The surrounding wall, in a cross-section of the processing chamber, includes: a first segment having a first width associated with a processing region for the substrate support; a second segment having a width greater than the first width that is further away from the plasma intake wall than the first segment.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 29, 2024
    Inventors: Yi-Yuan HUANG, Yi-Cheng LIU