Abstract: A level shifter includes a cross-coupled transistor pair, first through third biased transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first biased transistor pair is controlled by a first reference voltage. The second biased transistor pair is controlled by a pair of differential control voltages. The third biased transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second biased transistor pair.

Abstract: A display device includes a display area, a pixel array, a display medium layer, and a color filter layer. The display area includes a plurality of sub-pixel regions, and each of the sub-pixel regions has a length and a width that are substantially the same. The pixel array corresponds to the display area in position. The display medium layer is located on the pixel array. The color filter layer includes a plurality of color resists. The color resists are arranged along a first direction and a second direction different from the first direction. Two adjacent color resists arranged along the first direction have different colors, two adjacent color resists arranged along the second direction have different colors, and adjacent two of the color resists are spaced apart from each other.

Abstract: A color reflective display panel including a reflective display panel and a color filter array is provided. The color filter array is disposed on the reflective display panel. The color filter array includes a plurality of pixel units. Each pixel unit includes one or more first pixels having a first color, one or more second pixels having a second color, and one or more third pixels having a third color. The ratio of the area of the third pixels to the area of the pixel unit is less than one-third.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: An IC test method, comprising: electrically connecting a circuit board to a first IC; generating a first test signal to test the first IC; electrically connecting the circuit board to a first adaption board, and electrically connecting a second IC to the first adaption board, wherein a first connection mechanism between the first IC and the circuit board and a second connection mechanism between the second IC and the circuit board are different; and generating a second test signal to test the second IC by the control IC.

Abstract: A color filter module is provided. The color filter module is arranged on a display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes multiple sub-pixel regions arranged in an array. The color resist layer is arranged on the transparent substrate. The color resist layer includes multiple color resist units. The color resist units are respectively arranged across at least two sub-pixel regions, and the color resist units form a staggered array on the transparent substrate.

Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: A color filter array for a reflective display device includes a plurality of first filter arrays, a plurality of second filter arrays, and a plurality of third filter arrays. Each of the first filter arrays has a plurality of first filter patterns separated from each other. Each of the second filter arrays has a plurality of second filter patterns separated from each other. Each of the third filter arrays has a plurality of third filter patterns separated from each other. Each of the first filter arrays is adjacent to one of the second filter arrays and one of the third filter arrays.

Abstract: A method and apparatus are disclosed from the perspective of a network. In one embodiment, the method includes the network transmitting a Semi-Persistent Scheduling (SPS) configuration to a User Equipment (UE) for configuring a second Physical Downlink Shared Channel (PDSCH). The method also includes the network transmitting a configuration to the UE for configuring a first monitoring occasion for a first Physical Downlink Control Channel (PDCCH) and a second monitoring occasion for a second PDCCH, wherein the second PDCCH is associated with the first PDCCH. The method further includes the network not allowing the first PDCCH and the second PDCCH to schedule the UE with a first PDSCH partially or fully overlapping with the second PDSCH in time domain, wherein a last symbol of a later monitoring occasion among the first and the second monitoring occasion ends less than a processing threshold before a starting symbol of the second PDSCH.

Abstract: An electrophoretic display device, including an electrophoretic display panel and a display driving module, is provided. The display driving module is coupled to the electrophoretic display panel and is used for driving the electrophoretic display panel. The display driving module generates multiple first grayscale images according to multiple color pixel values of multiple color pixels corresponding to multiple colors of a color image. The display driving module captures multiple grayscale values of multiple locations of multiple first sub-pixels of the first grayscale images according to multiple locations of multiple mask sub-pixels corresponding to the colors in a mask image to generate multiple second grayscale images. The display driving module synthesizes the second grayscale images to generate a synthesized image. The display driving module drives the electrophoretic display panel according to the synthesized image.

Abstract: A display device which includes a display panel having a display surface, a transparent layer over the display panel and a color filter array over the transparent layer is provided. The color filter array includes yellow color filter elements, blue color filter elements and primary color filter elements. The yellow color filter elements project first regions on the display surface; the blue color filter elements project second regions on the display surface; and the primary color filter elements project third regions on the display surface. Each of the first regions is connected to at least one of the third regions, while each of the first regions is separated from any one of the second regions.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: An antenna system includes a first antenna element and a second antenna element. The first antenna element includes a first ground element, a first radiation element, a second radiation element, and a third radiation element. The first radiation element has a first feeding point. The second radiation element is coupled to the first ground element. The third radiation element is coupled to the first ground element. The third radiation element is adjacent to the first radiation element and the second radiation element. The second antenna element includes a second ground element, a fourth radiation element, a fifth radiation element, and a sixth radiation element. The fourth radiation element has a second feeding point. The fifth radiation element is adjacent to the fourth radiation element. The fifth radiation element is coupled through the sixth radiation element to the second ground element.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.